Patents Examined by Mujtaba M. Chaudry
  • Patent number: 10735030
    Abstract: A technique includes determining that a given memory device of a plurality of memory devices has failed and in response to the determination that the given memory device has failed, re-encoding a data unit associated with the given memory device. The data unit is associated with a payload and a symbol-based error correction code. The re-encoding includes determining a bit-based error correction code for the payload and replacing the data unit in the memory with the payload and the bit-based error correction code.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: August 4, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B. Lesartre, Harvey Ray, Kevin L. Miller, Chris Michael Brueggen, Martin Foltin
  • Patent number: 10733039
    Abstract: This disclosure relates to testing of integrated artificial intelligence (AI) circuit with embedded memory to improve effective chip yield and to mapping addressable memory segments of the embedded memory to multilayer AI networks at the network level, layer level, parameter level, and bit level based on bit error rate (BER) of the addressable memory segments. The disclosed methods and systems allows for deployment of one or more multilayer AI networks in an AI circuit with sufficient model accuracy even when the embedded memory has an overall BER higher than a preferred overall threshold.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Daniel H. Liu, Wenhan Zhang, Hualiang Yu
  • Patent number: 10735141
    Abstract: A system for reducing analog noise in a noisy channel, comprising: an interface configured to receive analog channel output comprising a stream of noisy binary codewords of a linear code; and a computation component configured to perform the following: for each analog segment of the analog channel output of block length: calculating an absolute value representation and a sign representation of a respective analog segment, calculating a multiplication of a binary representation of the sign representation with a parity matrix of the linear code, inputting the absolute value representation and the outcome of the multiplication into a neural network for acquiring a neural network output, and estimating a binary codeword by component-wise multiplication of the neural network output and the sign representation.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 4, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Amir Bennatan, Yoni Choukroun, Pavel Kisilev, Junqiang Shen
  • Patent number: 10725841
    Abstract: An integrated circuit (IC) includes an encoder circuit configured to receive input data including a plurality of data bits. A plurality of parity computation equations for a single error correct double error detect adjacent double error correct adjacent triple error detect (SECDEDADECADTED) Hamming code is received. A plurality of parity bits are computed using the plurality of parity computation equations. Write data including the data bits and the parity bits are provided to a write circuit. The write circuit writes the write data to a memory.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 28, 2020
    Assignee: XILINX, INC.
    Inventors: Kumar Rahul, Santosh Yachareni
  • Patent number: 10726936
    Abstract: A first group of data blocks of a memory sub-system is determined. The first group of data blocks is associated with a failure condition. Also, a second group of data blocks of the memory sub-system is determined. The second group of data blocks is not associated with the failure condition. User data is received and system data of the memory sub-system that is associated with the user data is generated. The system data is stored at the first group of data blocks that is associated with the failure condition by using a first programming operation. The user data is stored at the second group of data blocks that is not associated with the failure condition by using a second programming operation. The second programming operation is different from the first programming operation.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 28, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Roland J. Awusie
  • Patent number: 10719272
    Abstract: Multi-channel accessing of non-volatile memory. A controller uses three kinds of tables to manage cross-channel accessing areas and, accordingly, to access the non-volatile memory through multiple channels. Each cross-channel accessing area includes M storage units, where M is an integer greater than 1. For each cross-channel accessing area, the first table marks whether there is a need for storage unit substitution and points to substitution information. The substitution information is stored in the second table and the third table. For each cross-channel accessing area marked in the first table, the second table stores M bits corresponding to M storage units of the marked cross-channel accessing area for substitution indication, and related substitute storage unit indication is stored in the third table.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: July 21, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Liang-Cheng Chen
  • Patent number: 10712389
    Abstract: A number of embodiments include an apparatus comprising a memory array including a first memory bank and a second memory bank and a serializer/de-serializer coupled to the first memory bank and the second memory bank. The serializer/de-serializer may be configured to receive a scan vector from the first memory bank, send the scan vector to a device under test, receive scan test responses from the device under test, and send the scan test responses to the second memory bank. Scan control logic may be coupled to the serializer/de-serializer and the device under test. The scan control logic may be configured to control operation of the serializer/de-serializer and send a scan chain control signal to the device under test, wherein the scan chain control signal is to initiate performance of a scan chain operation using the scan vector.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Joshua E. Alzheimer
  • Patent number: 10707998
    Abstract: Disclosed is a method performed by a system of a wireless communication network for determining transmission conditions for a real-time media flow to be transmitted wirelessly to a first User Equipment, UE, residing in a first cell served by a first base station of the network. The method comprises obtaining radio network statistics of the first cell, the radio network statistics comprising radio network data for individual of a plurality of UEs in the first cell, UE throughput for individual of the plurality of UEs, and UE packet loss or packet delay for individual of the plurality of UEs, and obtaining, at a second time point occurring later in time than the obtaining of the radio network statistics, radio network data for the first UE.
    Type: Grant
    Filed: January 20, 2016
    Date of Patent: July 7, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Ying Wang, Jing Fu, Liping Wang
  • Patent number: 10705905
    Abstract: Selective use of a software path and hardware path help to provide fine-grained T10-PI support while maintaining IO operation efficiency for single IO read/write commands transferring multiple data segments. NVMe hardware capability (i.e. the hardware path) is always utilized for CPU-intensive CRC verification. NVMe hardware capability is utilized for application tag and reference tag verification whenever possible. Software running on a computing node (i.e. the software path) is used for application tag and reference tag verification and replacement when those functions cannot be implemented by the NVMe hardware.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 7, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Ningdong Li, Stephen Ives, Seema Pai, Scott Rowlands, James Guyer
  • Patent number: 10700819
    Abstract: Disclosed are a method and apparatus for processing a HARQ feedback and a method and apparatus for transmitting a HARQ feedback. The method for processing the HARQ feedback includes: receiving ACK/NACK information transmitted by a terminal simultaneously through a PUSCH and a PUCCH; determining whether a specified record exists in a historical record, the specified record being used for indicating that DCI corresponding to uplink grant information has been transmitted, and the uplink grant information being assigned to the terminal on a PDSCH; and decoding the ACK/NACK information on the PUSCH and/or the PUCCH if the specified record exists. Through the present disclosure, the problem that all data that has been successfully transmitted needs to be retransmitted due to a loss of DCI corresponding to the uplink grant information is solved.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: June 30, 2020
    Assignee: ZTE CORPORATION
    Inventors: Minggang Gao, Qingyu Ni, Li Bai, Jiaojiao Xue
  • Patent number: 10700703
    Abstract: To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Sanjeev N. Trika, Omesh Tickoo, Wei Wu
  • Patent number: 10700820
    Abstract: A modem chip for supporting combination of data repeatedly transmitted based on hybrid automatic repeat request (HARQ) is provided. The modem chip includes an HARQ combiner configured to perform a HARQ combination by combining retransmitted data with the previous HARQ data, the retransmitted data including retransmitted control channel data received via a control channel and retransmitted data channel data received via a data channel, the previous HARQ data corresponding to data received via the control channel and the data channel, the HARQ combination generating updated HARQ data, a memory configured to store the previous HARQ data and the updated HARQ data, and a memory controller configured to control transmission of the previous HARQ data and the updated HARQ data between the HARQ combiner and the HARQ memory.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 30, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-guen Ji, Hyoung-min Ko, Jung-eun Lee, Ki-joon Hong
  • Patent number: 10691535
    Abstract: A flash memory error correction method and apparatus is provided. The method includes determining a first data bit in a flash memory page, where the first data bit corresponds to different data respectively in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold and the data obtained by reading the flash memory page using the mth read voltage threshold; and then reducing a confidence level of the first data bit in the data obtained by reading the flash memory page using the (n+1)th read voltage threshold; and performing, according to an adjusted confidence level of the first data bit, error correction decoding on the data obtained by reading the flash memory page using the (n+1)th read voltage threshold. Present disclosure effectively improves a success rate of error correction decoding, thereby significantly improving performance of an SSD storage system.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 23, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yanxing Zeng, Jianqiang Shen, Gongyi Wang
  • Patent number: 10693499
    Abstract: Disclosed are an apparatus and a method for LDPC encoding suitable for highly reliable and low latency communication. The disclosed apparatus comprises: a second inner encoding module for outputting parity bits by means of single parity calculations and accumulation device calculations using bit strings outputted from a first inner encoding module; and the first inner encoding module for outputting a part of the parity bits by means of single parity check calculations for the bits output from a second outer module, and for outputting rest of the parity bit strings by means of single parity check calculations and accumulation device calculations, with a part of the parity bits output by the second inner encoding module as an additional input.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: June 23, 2020
    Assignee: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY
    Inventors: Kwang-Soon Kim, Ki Jun Jeon
  • Patent number: 10685159
    Abstract: In some examples, systems and methods may be used to improve functional safety of analog or mixed-signal circuits, and, more specifically, to anomaly detection to help predict failures for mitigating catastrophic results of circuit failures. An example may include using a machine learning model trained to identify point anomalies, contextual or conditional anomalies, or collective anomalies in a set of time-series data collected from in-field detectors of the circuit. The machine learning models may be trained with data that has only normal data or has some anomalous data included in the data set. In an example, the data may include functional or design-for-feature (DFx) signal data received from an in-field detector on an analog component. A functional safety action may be triggered based on analysis of the functional or DFx signal data.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 16, 2020
    Assignee: Intel Corporation
    Inventors: Fei Su, Prashant Goteti
  • Patent number: 10686617
    Abstract: A digital broadcasting system and method of processing data are disclosed. Herein, a method of processing data in a transmitting system includes creating a data group including a plurality of mobile service data packets, re-adjusting a relative position of at least one main service data packet of a main service data section, the main service data section including a plurality of main service data packets, and multiplexing the mobile service data of the data group and the main service data of the main service data section in burst units. Herein, a position of an audio data packet among the main service data packets of the main service data section may be re-adjusted. Also, a position of an audio data packet included in the main service data section may be re-adjusted based upon a multiplexing position of the main service data section.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: June 16, 2020
    Assignee: LG ELECTRONICS INC.
    Inventors: In Hwan Choi, Kook Yeon Kwak, Byoung Gill Kim, Jin Woo Kim, Hyoung Gon Lee, Jong Moon Kim, Won Gyu Song
  • Patent number: 10678667
    Abstract: Described herein are embodiments related to holdup self-tests in memory sub-systems for power loss operations. A processing device receives a request to perform a holdup self-test to detect a defect in a holdup circuit that powers the processing device and a memory component in the event of power loss. The processing device identifies a memory location of memory that is available and, responsive to detection of a loss of power, performs a continuous sequence of write operations to the memory location using holdup energy until all of the holdup energy is expended. After reboot, the processing device determines a number of the write operations that were successfully completed in the memory location before all of the holdup energy was expended. The processing device determines whether the number satisfies a defect criterion. Responsive to the responsive to the number satisfying the defect criterion, the processing device reports the defect associated with the holdup circuit.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 9, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Douglas Majerus, Brent Byron
  • Patent number: 10671328
    Abstract: A method begins by a processing module of a dispersed storage network (DSN) receiving a DSN retrieval request regarding a data object and performing a scoring function using properties of the DSN retrieval request and properties of DSN memory of the DSN to produce a storage scoring resultant. The method continues with the processing module identifying a set of primary storage units based on the storage scoring resultant and sending a set of retrieval requests to the set of primary storage units. When a primary storage unit does not provide a favorable response, using the storage scoring resultant to identify an alternative storage unit. When the alternative storage unit is identified, sending a corresponding retrieval request to the alternative storage unit.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 2, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Gary W. Grube, Jason K. Resch
  • Patent number: 10673828
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed or distributed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. The computing device receives first samples corresponding to inputs that characterize configuration of the DSN and receives second samples corresponding to outputs that characterize system behavior of the DSN. The computing device then processes the first and samples to generate a DSN model to generate predictive performance of the outputs based on various values of the inputs. In some instances, the DSN model is based on a neural network model that employs the inputs that characterize the configuration of the DSN and generates the outputs that characterize system behavior of the DSN.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 2, 2020
    Assignee: PURE STORAGE, INC.
    Inventor: Ilir Iljazi
  • Patent number: 10673467
    Abstract: An apparatus and a method. The apparatus includes a receiver including an input for receiving a codeword of length mj, where m and j are each an integer; a processor configured to determine a decoding node tree structure with mj leaf nodes for the received codeword and receive an integer i indicating a level at which parallelism of order m is applied to the decoding node tree structure; and m successive cancellation decoders (SCDs) configured to decode, in parallel, each child node in the decoding node tree structure at level i.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Mostafa El-Khamy, Hsien-Ping Lin, Jungwon Lee