Patents Examined by Mujtaba M. Chaudry
  • Patent number: 10659337
    Abstract: The present invention is directed to data communication systems and techniques thereof. More specifically, embodiments of the present invention provide a retimer module that includes plurality of communication lanes for interfacing with a host system and a line system. The retimer module includes a link monitor and cross point sections. The retimer also includes a management interface module. There are other embodiments as well.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 19, 2020
    Assignee: INPHI CORPORATION
    Inventors: Jamal Riani, Arash Farhoodfar, Sudeep Bhoja, Tarun Setya
  • Patent number: 10656999
    Abstract: Disclosed herein are methods, systems, and apparatus, including computer programs encoded on computer storage media, for storing blockchain data. One of the methods includes determining, by a blockchain node, one or more blocks that are infrequently visited; performing error correction coding of the one or more blocks to generate one or more encoded blocks; dividing, based on one or more predetermined rules, each of the one or more encoded blocks to a plurality of data sets; selecting one or more data sets from the plurality of data sets of each of the one or more encoded blocks based on the one or more predetermined rules; hashing the one or more data sets to generate one or more hash values corresponding to the one or more data sets; storing the one or more hash values; and deleting the one or more data sets.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: May 19, 2020
    Assignee: Alibaba Group Holding Limited
    Inventor: Haizhen Zhuo
  • Patent number: 10650905
    Abstract: An inspection apparatus includes a plurality of BIST circuits, each BIST circuit being configured to compare a test pattern output from an inspection target circuit with an expected value and output a signal indicating a comparison result, and a combining unit configured to generate one signal by performing a logical operation on a plurality of the signals indicating the comparison results which are output from the plurality of BIST circuits. The combining unit includes a plurality of level inspection circuits each configured to perform a level inspection of detecting a stuck-at fault. Each of the plurality of BIST circuits is connected to a corresponding one of the plurality of level inspection circuits.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Koichi Iwao
  • Patent number: 10635360
    Abstract: A method for execution by a compaction management system includes determining observed compaction information based on compaction observed in at least one storage device during an observed timeframe. An estimated compaction rate is generated for a first future timeframe based on the observed compaction information. An updated ingest rate is generated for the first future timeframe based on a current ingest rate and the estimated compaction rate. A first proper subset of a set of data to be written to the at least one storage device is generated based on the updated ingest rate. Storage of the first proper subset in the at least one storage device is facilitated during the first future timeframe. Storage of a remaining proper subset of the set of data in an elastic buffer is facilitated during the first future timeframe, where the elastic buffer utilizes a memory of the compaction management system.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ilya Volvovski, Andrew D. Baptist, Benjamin L. Martin, Praveen Viraraghavan, Ying Z. Guo, Jordan H. Williams
  • Patent number: 10628248
    Abstract: An aspect includes a method for dynamic random access memory (DRAM) scrub and error counting. A scrub operation is performed at memory locations in a DRAM. The performing includes, for each of the memory locations: receiving a refresh command at the DRAM; executing a read/modify/write (RMW) operation at the memory location, the executing including writing corrected bits to the memory location; and incrementing an error count in response to detecting an error during the executing. The method also includes comparing the error count to an error threshold. An alert is initiated in response to the error count exceeding the error threshold.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: April 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Marc A. Gollub, Warren E. Maule, Tony E. Sawan
  • Patent number: 10621091
    Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Antonino Mondello, Francesco Tomaiuolo, Salvatore Giove, Pierluca Guarino, Fabio Indelicato, Marco Ruta, Maria Luisa Gambina, Giovanni Nunzio Maria Avenia, Carmela Maria Calafato
  • Patent number: 10623138
    Abstract: Methods, systems, and devices that support an efficient sequence-based polar code description are described. In some cases, a wireless device (e.g., a user equipment (UE) or a base station) may transmit a codeword including a set of information bits encoded using a polar code or receive a codeword including a set of information bits encoded using a polar code. As described herein, the wireless device may determine the bit locations of the information bits in the polar code based on a partition assignment vector. Specifically, the wireless device may partition bit-channels for one or more stages of polarization and assign information bits to partitions based on the partition assignment vector. Once the bit locations of the information bits are determined, the wireless device may decode a received codeword or transmit an encoded codeword based on the determined bit locations of the information bits.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: April 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Yang Yang, Jing Jiang, Gabi Sarkis, Ying Wang, Wei Yang
  • Patent number: 10621041
    Abstract: Methods and apparatus to dynamically assign and relocate object fragments in distributed storage systems are disclosed. In some examples, the methods and apparatus encode an object with error correction coding to separate the object into fragments, create a first index indicative of storage nodes where the fragments of the object are to be stored, encode a second index into identifiers of the fragments of the object, the second index based on the first index, and store the fragments of the object and the corresponding second index encoded identifiers in the storage nodes based on the first index.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: April 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: Paul E. Luse, John Dickinson, Samuel Merritt, Clay Gerrard
  • Patent number: 10608668
    Abstract: Embodiments of this application provide a method for processing information bits in a wireless communication network. A device obtains a Polar encoded bit sequence, then divide the Polar encoded bit sequence into g groups that are of equal length N/g, wherein g is 32. The device block interleaves the g groups to obtain an interleaved bit sequence according to a sequence S, wherein the sequence S comprises: group numbers of the g groups, wherein a group whose number is 0 is the first element in the sequence S, wherein a group whose number is 12 is the 17th element in the sequence S, wherein a group whose number is 31 is the 32nd element in the sequence S, wherein the S is an integer and output the interleaved bit sequence.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: March 31, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Gongzheng Zhang, Ying Chen, Yunfei Qiao, Yourui Huangfu, Rong Li
  • Patent number: 10595333
    Abstract: A method and wireless transmit/receive unit (WTRU) for uplink transmission are disclosed. A WTRU receives configuration information. The configuration information includes logical channel priority information and a maximum number of hybrid automatic repeat request (HARQ) transmissions. For a transmission time interval (TTI), the WTRU identifies a HARQ process to use for uplink transmission for the TTI on a condition that an uplink grant is for the TTI. The WTRU selects data for uplink transmission for the TTI. For a new uplink transmission, data is allocated in decreasing order of priority based on the logical channel priority information. The WTRU initializes a transmission counter. The transmission counter indicates a number of transmissions associated with the selected data. The WTRU transmits the selected data over an uplink channel based on the uplink grant using the identified HARQ process.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: March 17, 2020
    Assignee: InterDigital Technology Corporation
    Inventors: Stephen E. Terry, Guodong Zhang
  • Patent number: 10594445
    Abstract: A method and system to improve the link budget of a wireless system using fast Hybrid Automatic Repeat Request (HARQ) protocol. In one embodiment of the invention, the Medium Access Control (MAC) logic in a base station determines whether the quality of the communication link with a mobile station is bad. When the MAC logic in the base station determines that the quality is bad, the base station uses a fast Hybrid Automatic Repeat Request (HARQ) protocol to indicate to the mobile station to send identical information to the base station in each of a plurality of successive or consecutive communication intervals before processing any received identical information from the mobile station. The fast HARQ protocol reduces the latency of receiving the identical information correctly, as compared with the current HARQ protocol.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 17, 2020
    Assignee: Apple Inc.
    Inventor: Aran Bergman
  • Patent number: 10592141
    Abstract: Apparatuses, systems, and methods are disclosed for error characterization for control of non-volatile memory. An apparatus may include an array of non-volatile memory cells and a controller. A controller may be configured to acquire an error characterization for a region of memory. Also, an error characterization may comprise information about one or more types of errors to which a region of memory is susceptible. A controller may be configured to assign a region of memory into a logical group based on an error characterization. Further, a logical group may comprise a plurality of regions of memory. Additionally, a controller may be configured to service a write request by striping data across multiple regions assigned to a logical group.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: March 17, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vinay Vijendra Kumar Lakshmi, Raghavendra Gopalakrishnan
  • Patent number: 10585744
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator pulls an operation from a first buffer and adjusts a receive credit value in a first window context operatively coupled to the hypervisor. The receive credit value to limit a first quantity of one or more first tasks in the first buffer. The hardware accelerator determines at least one memory address translation related to the operation having a fault. The switchboard forwards the operation with the fault memory address translation from the hardware accelerator to a second buffer. The operation and the fault memory address translation are flushed from the hardware accelerator, and the operating system repairs the fault memory address translation.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10580719
    Abstract: The semiconductor memory device includes first group dies including at least one buffer die, and second group dies including a plurality of memory dies stacked on the first group dies and conveying data through a plurality of TSV lines. Here, at least one of the plurality of memory dies includes a first type ECC circuit which generates transmission parity bits using transmission data to be transmitted to the first group die, and the buffer die includes a second type ECC circuit which corrects, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits and generates error-corrected data.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: March 3, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghun Kang, Kyoung-nam Ha, Hyungdong Kim, Jun-Phil Jung
  • Patent number: 10581596
    Abstract: Technologies for managing errors in a remotely accessible memory pool include a memory sled. The memory sled includes a memory pool having one or more byte-addressable memory devices and a memory pool controller coupled to the memory pool. The memory sled is to write test data to a byte-addressable memory region in the memory pool. The memory region is to be accessed by a remote compute sled. The memory sled is also to read data from the memory region to which the test data was written, compare the read data to the test data to determine whether a threshold number of errors are present in the read data, and send, in response to a determination that the threshold number of errors are present in the read data, a notification to the remote compute sled that the memory region is faulty.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Mark Schmisseur, Dimitrios Ziakas, Murugasamy K. Nachimuthu
  • Patent number: 10579452
    Abstract: Systems and methods are disclosed for performing rate matching when using general polar codes. In one embodiment, a method of generating a codeword includes receiving bits at a polar encoder and encoding the bits using polar encoder kernels. The polar encoder kernels include a first kernel and a second kernel. The first kernel receives a set of input q-ary symbols and modifies the set of input q-ary symbols according to a first kernel generator matrix to produce a set of output q-ary symbols. The second kernel receives a set of input l-ary symbols, where l does not equal q, and modifies the set of input l-ary symbols according to a second kernel generator matrix to produce a set of output l-ary symbols. For example, the first kernel may be a binary kernel and the second kernel may be a Reed-Solomon (RS) based kernel.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: March 3, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Wuxian Shi, Yiqun Ge, Nan Cheng, Ran Zhang
  • Patent number: 10573356
    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Uhn Cha, Young-Hun Seo, Kwang-Il Park, Seung-Jun Bae
  • Patent number: 10574274
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a first decoding on a codeword using a first decoder, determining a number of satisfied check nodes and a number of unsatisfied check nodes for a symbol value of the codeword for a decoding result of the first decoding, generating a soft log-likelihood ratio (LLR) for the symbol value based on the number of satisfied check nodes and the number of unsatisfied check nodes, and performing a second decoding using a second decoder with the soft LLR as an input to the second decoder.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 25, 2020
    Assignee: Nyquist Semiconductor Limited
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Patent number: 10572337
    Abstract: Hardware accelerator memory address translation fault resolution is provided. A hardware accelerator and a switchboard are in communication with a processing core. The hardware accelerator determines at least one memory address translation related to an operation having a fault. The operation and the fault memory address translation are flushed from the hardware accelerator including augmenting the operation with an entity identifier. The switchboard forwards the operation with the fault memory address translation and the entity identifier from the hardware accelerator to a second buffer. The operating system repairs the fault memory address translation. The operating system sends the operation to the processing core utilizing an effective address based on the entity identifier. The switchboard, supported by the processing core, forwards the operation with the repaired memory address translation to a first buffer and the hardware accelerator executes the operation with the repaired address.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Richard L. Arndt, Bartholomew Blaner
  • Patent number: 10567119
    Abstract: The present invention relates to retransmissions in a communications system. A method and system of reducing uplink retransmission delay of a radio communications system by introducing an uplink MAC ARQ layer of Node B is disclosed. Further, a MAC PDU data indicator for soft combining control in Node B and RLC PDU reordering is introduced.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 18, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Johan Torsner, Janne Peisa