Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.

Abstract: A stacked memory device (e.g., a high-bandwidth memory (HBM) device) having a storage component is disclosed. The stacked memory device can include a first logic die, one or more memory dies, a second logic die, and one or more storage dies. The first logic die is coupled with the one or more memory dies and the second logic die through TSVs. The second logic die is coupled with the one or more storage dies through additional TSVs. The first logic die can issue commands to the one or more memory dies that cause the one or more memory dies to perform operations (e.g., read/write operations). The first logic die can also issue commands to the second logic die that cause the second logic die to issue commands to the one or more storage dies to perform operations.

Abstract: A semiconductor device may include: a cell area in which a plurality of memory cells arranged in a first direction, a second direction and a third direction are disposed, the first direction and the second direction being parallel to an upper surface of a substrate and intersecting, and the third direction being perpendicular to the upper surface of the substrate; and a peripheral circuit area in which a word line driver connected to the plurality of memory cells through a plurality of word lines, a sense amplifier circuit connected to the plurality of memory cells through a plurality of bit lines, and a source line driver connected to the plurality of memory cells through a plurality of source lines, are disposed.

Abstract: The present disclosure configures a system component, such as memory sub-system controller, to perform empty page scan operations. The controller, in response to a request to perform an empty page scan operation, identifies a portion of a set of memory components that is empty and ready to be programmed. The controller generates an order in which to perform the empty page scan operation for a plurality of regions of the identified portion of the set of memory components. The controller determines whether a first region of the plurality of regions in the order fails the empty page scan operation before a second region of the plurality of regions is scanned. The controller terminates the empty page scan operation early to prevent performing the empty page scan operation for one or more remaining regions of the plurality of regions of the identified portion.

Abstract: Memory devices may be assigned enumeration values that uniquely identify the memory devices in a multi-memory device system. In some examples, the enumeration value is assigned by programming one or more fuses in the memory device. In some examples, a post-package repair operation may be used to program the fuses.

Abstract: A method for calibrating a read circuit of a magnetic memory device comprising the steps of setting resistances of first and second target resistors to a same value; setting resistances of first and second calibration resistors to a same minimum value; flowing a reference current through the first target resistor, the first calibration resistor, and a first input terminal of a sense amplifier in series; flowing a calibration current through the second target resistor, the second calibration resistor, and a second input terminal of the sense amplifier in series; determining a potential difference between the first and second input terminals; and if the second input terminal has a higher potential, incrementally increasing the resistance of the second calibration resistor until the first input terminal has a higher potential, or else incrementally increasing the resistance of the first calibration resistor until the second input terminal has a higher potential.

Abstract: In one embodiment, a semiconductor storage device includes a plurality of memory chips, at least one of the memory chips including a first controller configured to be shifted to a wait state of generating a peak current, before generating the peak current in accordance with a command. The device further includes a control chip including a second controller configured to search a state of the first controller and control, based on a result of searching the state of the first controller, whether or not to issue a cancel instruction for the wait state to the first controller that has been shifted to the wait state.

Abstract: An example non-transitory computer readable medium includes stored instructions which, when executed by a processor, cause the processor to convert an input clockwide pulse received from an upstream circuit running in a first clock domain into an output clockwide pulse that is synchronized to a second clock domain. The instructions further cause the processor to advance a count in response to the output clockwide pulse that is synchronized to the second clock domain.

Abstract: A storage device including: a non-volatile memory comprising a plurality of memory cells, wherein the plurality of memory cells comprises a target memory cell; and a storage controller: wherein the storage controller is configured to: read the target memory cell at a plurality of target read times to obtain a plurality of target voltages, select a threshold model corresponding to the target memory cell from among a plurality of threshold models, and generate data corresponding to the target memory cell by providing the plurality of target voltages to the threshold model.

Abstract: An on-chip static RAM (SRAM) is disclosed. In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows, a read bit line for each column of the array of memory cells, and an output latch to store a bit for one of the array of memory cells when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell in the column is connected to the read bit line for that column and the output latch includes a transistor that does not allow the read bit line for the column corresponding to the one of the array of memory cells to pre-charge when a data latch in the output latch is in a high state.

Abstract: An integrated circuit includes a first input/output lane comprising first external terminals and first driver circuits. The first driver circuits exchange signals with a first external device through the first external terminals as part of a first external interface. The first input/output lane is part of a sub-bank in an input/output bank that implements at least a part of the first external interface. The integrated circuit includes a second input/output lane comprising second external terminals and second driver circuits. The second driver circuits exchange signals with a second external device through the second external terminals as part of a second external interface. The second input/output lane is part of the sub-bank in the input/output bank that implements at least a part of the second external interface.

Abstract: A system includes a read amplifier having a first input, a second input, a first output, and a second output. The read amplifier includes a first inverter having an input and an output, wherein the output of the first inverter is coupled to the first output of the read amplifier, and a second inverter having an input and an output, wherein the output of the second inverter is coupled to the second output of the read amplifier and the input of the first inverter, and the input of the second inverter is coupled to the output of the first inverter. The system also includes one or more first fuses coupled to the first input of the read amplifier, and one or more second fuses coupled to the second input of the read amplifier.

Abstract: A memory with e-fuses includes a receiving circuit and a plurality of e-fuse groups. Each e-fuse group of the e-fuse groups is coupled to the receiving circuit through a corresponding bus group. The receiving circuit receives a plurality of blown signal sets each time and transmits each of the blown signal sets to a e-fuse group, and predetermined e-fuses of the e-fuse group are blown according to the each of the blown signal sets to adjust predetermined settings of the memory, and the each of the blown signal sets only corresponds to the e-fuse group. A number of the plurality of blown signal sets is not greater than a number of the e-fuse groups.

Abstract: A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.

Abstract: The present disclosure relates to a memory device including a sense amplifier, wherein the amplifier comprises a first inverter, wherein an input and an output of the inverter are coupled to a first transistor configured to be switched on during a step of pre-charging of a memory cell.

Abstract: Apparatuses and methods for row hammer counter mat. A memory array may have a number of memory mats and a counter memory mat. The counter mat stores count values, each of which is associated with a row in one of the other memory mats. When a row is accessed, the count value is read out, changed, and written back to the counter mat. In some embodiments, the count value may be processed within access logic of the counter mat, and a row hammer flag may be provided to the bank logic. In some embodiments, the counter mat may have a folded architecture where each sense amplifier is coupled to multiple bit lines in the counter mat. The count value may be used to determine if the accessed row is an aggressor so that its victims can be refreshed as part of a targeted refresh.

Abstract: Methods, systems, and devices for minimum memory clock estimation procedures are described. For instance, a device, such as a host device, may truncate a value of a first parameter associated with a first duration for a clock coupled with a memory array to perform a clock cycle and may determine a value of a second parameter that is inversely proportional to a combination of the truncated first parameter and a correction factor. The device may determine a quantity of clock cycles associated with a second duration for accessing one or more memory cells of the memory array based on adjusting a third parameter associated with the second parameter. The device may access the one or more memory cells of the memory array based on the determined quantity of clock cycles.

Abstract: Apparatuses and methods increased reliability row hammer counts. Each word line of a memory may have an associated count value, stored in memory cells of the word line. Information in memory cells may be prone to change, such as from neutron strike. A counter circuit may decrease the count value each time the word line is accessed, since a decreasing count will tend to overestimate accesses due to error. A count error correction circuit may check the count value against redundant information and correct the count value if there is an error. Decreasing counts and count error correction may be used together to further increase reliability.

Abstract: Examples of the present application disclose a memory device, an operation method, a memory system, and a computer system.

Abstract: An apparatus is provided that includes a memory structure including non-volatile memory cells that include a plurality of columns, each column including a column address, and a column redundancy system coupled to the memory structure and a clock signal. The column redundancy system is configured to in a first cycle of the clock signal first compare a first input column address to a first pair of defective column addresses received during an immediately preceding cycle of the clock signal, second compare the first input column address to a second pair of defective column addresses received during the first cycle of the clock signal.