Patents Examined by Muna A Techane
  • Patent number: 11328752
    Abstract: A self-timed sensing architecture for reading a selected cell in an array of non-volatile cells is disclosed. The sensing circuitry generates a signal when a stable sensing value has been obtained from the selected cell, where the stable sensing value indicates the value stored in the selected cell. The signal indicates the end of the sensing operation, causing the stable sensing value to be output as the result of the read operation.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: May 10, 2022
    Assignee: Silicon Storage Technology, Inc.
    Inventor: Massimiliano Frulio
  • Patent number: 11328783
    Abstract: A semiconductor device includes a first word line configured to perform a writing operation or a programing operation, a second word line configured to perform a read operation, a first switching device including a first gate electrode and a first node, a second switching device comprising a second gate electrode and a second node, an electrical fuse (e-fuse) disposed between the first node and the second node, and a diode coupled to the first node and the first word line, wherein the first gate electrode and the second gate electrode are coupled to the second word line.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: May 10, 2022
    Assignee: KEY FOUNDRY CO., LTD.
    Inventors: Jong Min Cho, Sung Bum Park, Kee Sik Ahn, Seong Jun Park
  • Patent number: 11315611
    Abstract: A memory system includes a stacked memory device and a controller. The stacked memory device includes a base die and a plurality of memory dies stacked on the base die. Each of the plurality of memory dies has a plurality of channels, and the base die is configured to function as an interface for transmitting signals and data of the pluralities of channels. The controller controls the stacked memory device such that first and second data move control operations are sequentially performed to transmit moving data from a target channel of the pluralities of channels to a destination channel of the pluralities of channels. The first data move control operation is performed to store the moving data in the target channel into the base die, and the second data move control operation is performed to write the moving data stored in the base die into the destination channel.
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventor: Choung Ki Song
  • Patent number: 11308997
    Abstract: A memory device includes a substrate, a controller disposed on the substrate and providing an external interface, and a plurality of flash memory dies connected to the controller through an internal interface. The external interface includes at least a bypass pin, a mode selection pin, and a data pin, and is used by an external host to direct access the plurality of flash memory dies through the controller. The bypass pin is used to enable the controller to enter in a direct access state in which the mode selection pin and the data pin are operational; and the mode selection pin is used to trigger the controller to receive a mode code on the data pin and to receive a mode code value on the data pin. The mode code indicates one of a plurality of predetermined input-output modes of the controller in the direct access state, and the mode code value determining information under the predetermined input-output mode indicated by the mode code.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: April 19, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xiaodong Xu, Yi Chen
  • Patent number: 11302366
    Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port in the input mode, the multi-address read operation including receiving a first address and a second address using the at least one signal line in the input mode before switching to the output mode, switching to the output mode and outputting data identified by the first address using the at least one signal line.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: April 12, 2022
    Inventors: Kuen-Long Chang, Su-Chueh Lo, Yung-Feng Lin
  • Patent number: 11302370
    Abstract: Data is synchronized when transmitted from a circuit operated at first frequency to another circuit operated at second frequency. A synchronization method includes storing data write pointers in a line, storing data input from a source at first frequency at a location in a data buffer designated by the write pointer at one end of the line, taking out the write pointer at the one end from the line to store it in the synchronization buffer, synchronizing a validation signal input from the input source at first frequency to second frequency, reading out the write pointer stored in the synchronization buffer when the validation signal is synchronized, adding completion information that indicates completion of synchronization to the data stored at the location in the data buffer designated by the read out write pointer, and reading out, from the data buffer, the data to which the completion information is added.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: April 12, 2022
    Inventor: Shinichi Iwasaki
  • Patent number: 11295922
    Abstract: Fuse programming circuits, devices and methods. In some embodiments, a fuse circuit can include a fuse pad configured to receive a voltage, a fuse having a first end coupled to the fuse pad and a second end coupled to a switching element configured to enable a current to pass from the fuse pad to a ground potential.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 5, 2022
    Assignee: Skyworks Solutions, Inc.
    Inventor: Bo Zhou
  • Patent number: 11295815
    Abstract: An integrated circuit device includes a plurality of word lines, a string selection line structure stacked on the plurality of word lines, and a plurality of channel structures extending in a vertical direction through the plurality of word lines and the string selection line structure. The string selection line structure includes a string selection bent line including a lower horizontal extension portion extending in a horizontal direction at a first level higher than the plurality of word lines, an upper horizontal extension portion extending in the horizontal direction at a second level higher than the first level, and a vertical extension portion connected between the lower horizontal extension portion and the upper horizontal extension portion.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: April 5, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwanyong Kim, Sunil Shim, Wonseok Cho
  • Patent number: 11295794
    Abstract: According to one embodiment, a memory system includes a plurality of memory packages, on-die termination (ODT) circuits, and a controller. The plurality of memory packages are coupled by a common bus and arranged in groups, each group includes a pair of memory packages facing each other, and each memory package includes a plurality of memory chips. The ODT circuits are respectively disposed in the memory packages. The ODT circuits are on/off controlled based on an asserted state of a chip enable signal CEn acquired using a periodic signal of at least two cycles.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: April 5, 2022
    Inventor: Kiyotaro Itagaki
  • Patent number: 11289131
    Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: March 29, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Benjamin Tsien, Alexander J. Branover, Alan Dodson Smith, Chintan S. Patel
  • Patent number: 11282561
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: March 22, 2022
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Patent number: 11270780
    Abstract: A circuit includes an OTP cell, an NVM cell, and a bit line coupled to the OTP cell, the NVM cell, and a first input terminal of an amplifier. The amplifier is configured to generate an output voltage based on a signal on the bit line, an ADC is configured to generate a digital output signal based on the output voltage, and a comparator includes a first input port coupled to an output port of the ADC and is configured to output a data bit responsive to a comparison of the digital output signal to a threshold level received at a second input port.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 8, 2022
    Inventor: Chih-Min Liu
  • Patent number: 11264065
    Abstract: A data transceiver device and an operation method are provided. The data transceiver device receives input data and transmits output data. The data transceiver device includes a buffer circuit, a storage circuit, a timing circuit and a control circuit. The buffer circuit is configured to store input data. The storage circuit is configured to store the output data. The timing circuit is configured to generate a time-out signal according to the set time. The control circuit is configured to process the input data to generate the output data, to store the output data in the storage circuit, and to transmit the output data according to an output data threshold value and the time-out signal. The control circuit adjusts the set time and/or the output data threshold value based on an initial condition and the state of the buffer circuit.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: March 1, 2022
    Inventors: Zhen-Ting Huang, Chun-Hao Lin, Er-Zih Wong, Shih-Chiang Chu
  • Patent number: 11264064
    Abstract: A data driving circuit may include a trigger circuit and a pre-driver. The trigger circuit may be configured to block a remaining signal path among a plurality of signal paths for transmitting data except for a signal path corresponding to a currently selected driving strength. The pre-driver may be configured to drive data, which are transmitted through the signal path corresponding to the currently selected driving strength, using an impedance determined in accordance with a plurality of impedance control codes.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Eun Ji Choi
  • Patent number: 11257529
    Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yangsung Joo, Hidekazu Noguchi
  • Patent number: 11250315
    Abstract: An electrochemical device includes an electrochemical cell and an electric circuit. The electrochemical cell comprises a first solid component and a second solid component. The two solid components comprise same chemical elements but have different concentrations of at least one type of the chemical elements. A solid electrolyte is arranged between the two solid components. The solid electrolyte is a dielectric material. The electric circuit is connected to the electrochemical cell. The electrochemical cell may be operated according to a redox process, so as to exchange chemical elements of the at least one type between the first solid component and the second solid component and thereby change an electrical conductance of each of the two solid components.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: February 15, 2022
    Inventors: Valeria Bragaglia, Patrick Ruch, Antonio La Porta, Jean Fompeyrine, Stefan Abel
  • Patent number: 11250906
    Abstract: The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus (10) for compensating for radiation tolerance comprises: a voltage value acquisition unit (11) that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit (12) that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit (13) that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: February 15, 2022
    Inventors: Yoshiharu Mori, Masaki Kusano, Daisuke Matsuura, Daisuke Kobayashi, Kazuyuki Hirose, Osamu Kawasaki
  • Patent number: 11244709
    Abstract: Embodiments provide a write operation circuit, a semiconductor memory, and write operation method. The write operation circuit includes: a data determination module that determines whether to flip an input data of the semiconductor memory depending on the number of high data bits in the input data so as to generate a flip flag data and a first intermediate data; a data buffer module that determines whether to flip a global bus according to a second intermediate data, where the second intermediate data is an inverted data of the first intermediate data; a data receiving module that decodes the global bus data according to the flip flag data and writes the decoded data into a memory bank of the semiconductor, where the decoding including determining whether to flip the global bus data; and a precharge module that sets the initial state of the global bus to low.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: February 8, 2022
    Inventor: Liang Zhang
  • Patent number: 11244739
    Abstract: Methods and apparatuses with counter-based reading are described. In a memory device, a memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Umberto Di Vincenzo, Riccardo Muzzetto, Ferdinando Bedeschi
  • Patent number: 11232842
    Abstract: A method for determining an optimal threshold of a nonvolatile memory device, the method including: reading a page from a nonvolatile memory device with a default threshold and attempting to hard decode the page using the default threshold; reading the page two more times with a predetermined offset voltage when the hard decoding fails and attempting to soft decode the page using the default threshold; approximating an empirical distribution of successfully decoded bits with a Gaussian distribution for each level; finding an intersection of the Gaussian distributions; and setting the intersection as a new reading threshold and reading the page again with the new reading threshold.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: January 25, 2022
    Inventors: Elisha Halperin, Evgeny Blaichman, Amit Berman