Abstract: An offset calibration training method for adjusting a data receiver offset and a memory device therefor are provided. A method of performing a data receiver offset calibration includes storing a first parameter code, which is used to set a default data receiver offset calibration for the data receiver offset calibration, in a mode register, storing a second parameter code, which is used to set an optional data receiver offset calibration for the data receiver offset calibration, in the mode register, training the default data receiver offset calibration based on the first parameter code for the data receiver offset calibration, and training the optional data receiver offset calibration based on the second parameter code for the data receiver offset calibration.

Abstract: The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Abstract: A pulse generator, an Error Check and Scrub (ECS) circuit and a memory are provided. The pulse generator includes: a delay circuit configured to receive an ECS command signal, perform delay processing on the ECS command signal, and output a delay command signal, the delay between the ECS command signal and the delay command signal being a first preset value; and a latch circuit configured to receive the ECS command signal and the delay command signal, perform latch processing based on the ECS command signal and the delay command signal, and output an ECS pulse signal. The pulse width of the ECS command signal is provided with a plurality of values, and the pulse width of the ECS pulse signal is the first preset value.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.

Abstract: A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.

Abstract: An anti-fuse cell structure includes: a first anti-fuse transistor having a first end and a second end; a first selection transistor having a first end and a second end, the first end of the first selection transistor being electrically connected to the second end of the first anti-fuse transistor; and a Blow Enable (BE) line electrically connected to a first end of the first anti-fuse transistor, and configured to perform programming operation on the first anti-fuse transistor.

Abstract: Disclosed is logic device using spin orbit torque. Two magnetic tunnel junctions have mutually opposite magnetization directions. The direction of the current flowing through the non-magnetic metal layer acts as an input, and the resistance states of the magnetic tunnel junctions are determined by the input program currents. Various logic devices are implemented by a method of setting the input program current to a logic high or a logic low.

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) memory structure. The IC memory structure includes a first conductor over a substrate and a second conductor over the first conductor. The first conductor is vertically separated from the second conductor by an isolation structure. A first channel structure is arranged on a sidewall of the isolation structure. The first channel structure is vertically between the first conductor and the second conductor. A vertical gate electrode is disposed along sidewalls of the first conductor, the second conductor, and the first channel structure. The sidewall of the first channel structure faces away from the isolation structure.

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

Abstract: Devices and methods include transmitting loopback signals for monitoring operation of a memory device. In some embodiments, a memory device may receive a system clock signal from a host device and may generate an internal clock signal based at least in part on the system clock signal. In some embodiments, the memory device may generate a loopback signal based at least in part on the internal clock signal and may transmit the loopback signal via a loopback datapath associated with the memory device. A host device may compare the internal clock signal and the system clock signal to determine a fidelity of the internal clock signal. Termination values of the memory device may be adjusted based on the determined fidelity of the internal clock signal.

Abstract: A field of memory technologies and a reading circuit for a differential one time programmable (OTP) memory including a first and second memory cells in a differentially symmetrical structure, the reading circuit connects between the first and second memory cells and includes: a detector having a first and second connected to respective first and second memory cells, configured to detect one of a resistance value of a first or second fuse of respective first and second memory cells, and a resistance difference between the first and second fuse after a burn-in operation of the first or second memory is completed; and a latch connected to the detector, provides a readout data according to one of the resistance value of the first or second fuse, and the resistance difference. The reading circuit may both read out data normally and detect a resistance value of the fuse.

Abstract: In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: The present disclosure provides an electronic device and a driving method. The electronic device comprises: a sensitivity amplifier and a voltage adjustment circuit. The sensitivity amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, a second N-type transistor, and a control circuit. The control circuit is connected to the third node, the fourth node, and a preset voltage terminal. A first control signal terminal responds to the signal of the first control signal terminal to connect the preset voltage terminal and the third node and the fourth node. The preset voltage terminal inputs a preset voltage signal. The electronic device write a preset voltage signal of a suitable size to the sensitivity amplifier through the voltage adjustment circuit, so that the sensitivity amplifier has an appropriate voltage difference between the bit line and the complementary bit line during offset elimination.

Abstract: A memory device including a plurality of nonvolatile memory chips each including a status output pin and a buffer chip configured to receive a plurality of internal state signals, which indicate states of the plurality of nonvolatile memory chips, from the status output pins and output an external state signal having a set period on the basis of the internal state signals indicating a particular state, wherein in a first section of the external state signal having the set period, a duty cycle of the external state signal determines depending on an identification (ID) of the nonvolatile memory chip which outputs the internal state signal indicating the particular state among the plurality of nonvolatile memory chips.

Abstract: A multi-stage method for programming an n-bit memory cell array using a fixed number of data latches is disclosed. The fixed number of data latches may be a reduced number of data latches in sense amplifier and data latch (SADL) peripheral circuitry than is required by existing programming techniques. As such, the die area taken up by the SADL circuitry can be reduced, which in turn, reduces overall chip area. The multi-stage programming method may include utilizing a first data latch to receive and store program page data and utilizing a second data latch to store bit information indicating which cells are to be targeted for the multi-stage programming. At each program stage, a respective program loop may be performed with respect to each threshold voltage distribution generated during a prior program stage to create two new threshold voltage distributions from the prior distribution.

Abstract: A circuit includes a plurality of anti-fuse cells coupled to a first selection circuit, a plurality of magnetic random-access memory (MRAM) cells coupled to a second selection circuit, an amplifier including a first input terminal coupled to each of the first and second selection circuits, an analog-to-digital converter (ADC) including input terminals coupled to output terminals of the amplifier, and a comparator including a first input port coupled to an output port of the ADC. The amplifier, ADC, and comparator are configured to output data bits from the comparator responsive to current levels received from the first selection circuit at the first input terminal of the amplifier and first voltage levels received from the second selection circuit at the first input terminal of the amplifier.

Abstract: A reference voltage generating circuit according to an embodiment includes: an original reference voltage generating unit that generates an original reference voltage; and a reference voltage correcting unit that decreases the original reference voltage as the temperature rises and outputs the original reference voltage as a reference voltage to a sense amplifier, and thus it is possible to perform highly reliable operation while the influence of the temperature is reduced.