Abstract: A semiconductor integrated circuit includes: a power supply pin configured to receive an external power supply voltage; a fuse memory circuit including a fuse element; and a power supply circuit, whose output is connected to the fuse memory circuit, configured to receive the external power supply voltage, the power supply circuit being switchable in response to a control signal between (i) a first state in which an internal power supply voltage of a first voltage level, which is capable of cutting the fuse element, is supplied to a power supply line of the fuse memory circuit and (ii) a second state in which the internal power supply voltage of a second voltage level lower than the first voltage level, which is incapable of cutting the fuse element, is supplied to the power supply line of the fuse memory circuit.

Abstract: Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.

Abstract: Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.

Abstract: A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a bit line clamping voltage; and perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones identified.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to apply a pre-programming pulse of a pre-program voltage to a selected one and at least one neighboring one of the plurality of word lines in a pre-program operation. The control means is also configured to apply each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the plurality of data states to the selected one of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation.

Abstract: A semiconductor device includes a memory cell including a first transistor, a second transistor, and a resistor. Each of the first transistor and the second transistor is operatively coupled to the resistor in series. The second transistor is formed below the resistor such that the second transistor provides heat to the resistor when the memory cell is being programmed.

Abstract: A semiconductor memory device includes memory cell transistors and a control circuit. The control circuit is configured to set a threshold voltage of each memory cell transistor to be in one of voltage ranges to store multi-bit data in each memory cell transistor. The voltage ranges include a first range corresponding to a first multi-bit value, a second range lower than the first range and corresponding to a second multi-bit value, and a third range that is the lowest. When a target memory cell transistor in which data of the second multi-bit value is to be written currently stores data of the first multi-bit value, the control circuit is configured to apply a first voltage to a gate of the target memory cell transistor, to shift the threshold voltage of the target memory cell transistor to be in the second range without dropping into the third range.

Abstract: Examples herein describe memory lifecycle state sensors. A memory lifecycle state sensor includes a memory and a processor. The processor is configured to write a first value to a cell of the memory at a first voltage, and the cell is storing a second value written to the cell at a second voltage that is greater than the first voltage. A value is read from the cell and compared with the first value. An indication of a lifecycle state for the cell is generated based on comparing the value with the first value, the first voltage, and the second voltage.

Abstract: To program MRAM memory cells current must flow from the memory cell's corresponding bit line to its corresponding word line or from the word line to bit line. To accomplish this, the bit line and word line decoders must be capable of sourcing current (when driving a line positive) and sinking current (when pulling the line negative) to account the memory cell's bipolar nature. Consequently, the decoders must be bipolar. For the negative select switches NMOS devices are used and for the positive select switches PMOS switches are used. To reduce layout area and routing, the negative select switches and positive select switches are separately grouped, with a subset of the positive select switches located between subsets of the negative select switches and vice-versa. The connection for the decoder switches are routed to a central hook-up region for connection to the control lines of the cross-point array.

Abstract: One-time programmable (OTP) bit-cell for an integrated circuit (IC) that includes an OTP element, such as a fuse or antifuse, coupled in electrical series with a selector that comprises a Schottky junction. The selector may comprise a metal-semiconductor-metal (MSM) material stack operable as transient voltage suppression (TVS) device that experiences electrical breakdown at a voltage below a programming voltage of the OTP element. In response to a programming voltage, the MSM stack may breakdown and pass a transient current sufficient for programming the OTP element. In response to a lower (e.g., read) voltage, the MSM stack may breakdown and pass a transient current insufficient for programming, but sufficient to sense a state of the OTP element. In response to an even lower (e.g., half-read) voltage, the MSM stack may present a very high OTP bit-cell input impedance, reducing leakage and/or sneak path currents within an array of such bit-cells.

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: Multiple guard rows are included in a region of memory. Accesses to the region of memory are monitored and a revolver technique using the guard rows is enabled in response to the number of accesses to the region of memory equaling or exceeding a threshold amount within a given interval of time. The guard rows are moved around the region of memory with one or more non-guard rows being situated between the guard rows. A guard row refers to a row of the region of memory that stores invalid data, whereas the one or more non-guard rows store valid data. After being moved, accesses to the region of memory are monitored and after another threshold number of accesses to the region of memory the guard rows are moved again. This process continues with the guard rows being moved, e.g., in a circular manner, through the region of memory.

Abstract: A device includes a memory cell including a first transistor and a second transistor disposed on a frontside of a substrate, the substrate having a first area and a second area. The memory device includes a first interconnect structure disposed on a backside of the substrate. One S/D terminal of the first transistor is coupled to one S/D terminal of the second transistor, with the other S/D terminal of the second transistor coupled to the first interconnect structure through a first via structure in the first area. The memory device includes second via structures and a third via structure both disposed in the second area and each coupled to the first interconnect structure. The first via structure and the second via structures each have a cross-sectional area that is different from that of the third via structure.

Abstract: Examples of the present disclosure provide a memory device, memory system, memory controller and operating method thereof. The memory device includes a memory cell with multiple storage bits, a preset number of the memory cells form one code word, and the multiple storage bits correspond to multiple pages respectively. The multiple stages include a first stage and a second stage. The peripheral circuit of the memory device is configured to: obtain a predicted valley voltage in the first stage in accordance with the corresponding first result at the target read voltage in the first stage; obtain the predicted valley voltage in the second stage in accordance with the predicted valley voltage in the first stage; and perform a first read operation on at least one code word with the predicted valley voltage in the first stage and the predicted valley voltage in the second stage.

Abstract: A memory device includes several computing memory cells each storing a weight value and comprising a first and a second switch elements and a first and a second resistors. The first switch element receives a sensing current and a first input signal related to the input value. The first resistor selectively receives the sensing current through the first switch element in response to the first input signal. The second switch element receives the sensing current and a second input signal related to the input value. The second resistor selectively receives the sensing current through the second switch element in response to the second input signal. When the sensing current flows through the first resistor or the second resistor, the computing memory cell generates a first voltage difference or a second voltage difference corresponding to an output value equal to product of an input value and a weight value.

Abstract: In an apparatus, a memory controller, a memory device, and a method for switching frequencies of clock signals to reduce power consumption, when the memory device performs an internal operation according to a command of the memory controller, a frequency of a clock signal of the memory controller is changed. The memory controller switches the frequency of the clock signal to a low frequency according to assertion of a status signal that indicates a busy operation status of the memory device according to the command, and switches the frequency of the clock signal to a high frequency according to de-assertion of the status signal that indicates a ready operation status of the memory device.

Abstract: Embodiments of the present disclosure relate to a SRAM (static random access memory) bit cell. More particularly, embodiments of the present disclosure relate to a single port, 8T SRAM cell with write enhance pass gate transistors. Particularly, two write enhance pass gate transistors are parallelly connected with the pass gate transistors in a standard 6T SRAM cell. The write enhance pass gate transistors are independently controlled from the pass gate transistor using a write enhance word line. In some embodiments, the single port, 8T SRAM cell according to the present disclosure may be implemented by stacked complementary FETs. Empty or dummy PMOS transistors in a standard 6T stacked CFET SRAM cell are used as pass gate transistors or write enhance pass gate transistors.

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: Processing logic in a memory device receives a calibration scan command associated with the memory device. In response to the calibration scan command, execution of a set of read operations at a plurality of read voltage levels on the memory device is caused. In response to the calibration scan command, a set of bit counts is identified, where each bit count of the set of bit counts corresponds to a respective bin of a set of bins associated with the plurality of read voltage levels. Based on the bit count corresponding to each bin of the set of bins, a bin having a lowest bit count is identified.

Abstract: A memory device includes a memory cell array including a plurality of memory cells, a temperature sensor configured to measure an internal temperature and generate a temperature compensation code corresponding to the internal temperature, a voltage control circuit configured to generate a conversion temperature code converted from the temperature compensation code, and a voltage generation circuit configured to output a compensation voltage obtained by compensating for a level of a voltage used in an operation on the memory cell array responsive to the conversion temperature code. The temperature sensor and the voltage control circuit are may be located at different positions relative to the memory cell array.