Patents Examined by Muna A Techane
  • Patent number: 11688481
    Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Jimmy Lee, Yih Wang
  • Patent number: 11688452
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: June 27, 2023
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Patent number: 11682438
    Abstract: A data writing control device includes a control signal generator, a data strobe enable signal generator and a data strobe index generator. The control signal generator receives a write command, a preamble setting value and a latency setting value, and generates an internal write pulse and preamble information according to the write command, the preamble setting value and the latency setting value. The data strobe enable signal generator is coupled to the control signal generator and generates a data strobe pipeline enable signal according to the internal write pulse and the preamble setting value. The data strobe index generator is coupled to the data strobe enable signal generator, and generates a plurality of data strobe indexes according to the data strobe pipeline enable signal and the preamble information.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: June 20, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Tien Te Huang, Yu Hsin Chen
  • Patent number: 11676676
    Abstract: In some aspects of the present disclosure, a memory array includes: a plurality of memory cells; and a plurality of logic gates, each of the plurality of logic gates having a first input, a second input, and an output gating a corresponding one of the plurality of memory cells, wherein the first input of each of the plurality of logic gates of a first subset is coupled to a first bit select line.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: June 13, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Perng-Fei Yuh
  • Patent number: 11676659
    Abstract: A method for operating a memory device includes initiating an access operation to a corresponding row of an array of bit cells of the memory device. Responsive to an expansion mode signal having a first state, the method further includes dynamically operating each column of a plurality of columns of the array to access each bit cell of a corresponding row within the plurality of columns during the access operation. Alternatively, responsive to the expansion mode state signal having a second state different than the first state, the method includes dynamically operating each column of a first subset of columns of the plurality of columns to access each bit cell of a corresponding row within the first subset of columns during the access operation, and maintaining each column of a second subset of columns of the plurality of columns in a static state during the access operation.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: June 13, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Wuu, Martin Paul Piorkowski
  • Patent number: 11670390
    Abstract: A re-programmable integrated circuit (IC) includes a plurality of non-volatile memory elements, each including a fuse portion initially configured to have either a first resistance value or a second resistance value. Re-programming circuitry includes a controllable element coupled to each fuse portion and selectively operable to cause an electrical current to flow through the fuse portion sufficient to cause that fuse portion to transition to an altered state having a resistance value greater than the first and second resistance values. Reference resistance circuitry is configurable between an initial state and a re-programmed state.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: June 6, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Michael Allen Ball, Anand Seshadri
  • Patent number: 11670351
    Abstract: Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: June 6, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Arun Babu Pallerla, Anil Chowdary Kota, Changho Jung, Chulmin Jung
  • Patent number: 11670393
    Abstract: A semiconductor device includes a flag generation circuit configured to receive region fuse data and used fuse data which are generated from a fuse set selected based on a fuse set selection signal among from fuse sets and generate a bank resource flag to control a repair operation for a bank on which a repair operation has not been performed, based on the region fuse data and the used fuse data. The semiconductor device also includes a repair control circuit configured to control the repair operation for banks sharing the fuse sets based on the bank resource flag.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: June 6, 2023
    Assignee: SK hynix Inc.
    Inventors: Dong Beom Lee, Eun Je Kim, Hyeong Soo Jeong
  • Patent number: 11664058
    Abstract: A memory device and an operation method thereof are provided. The operation method includes: in a first phase, selecting a global signal line, selecting a first string select line, unselecting a second string select line, selecting a first word line, and unselecting a second word line; sensing during a second phase; in a third phase, keeping voltages of the global signal line, the selected first word line and the unselected second word line, unselecting the first string select line and selecting the second string select line to switch voltages of the first and the second string select lines; and sensing during a fourth phase.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: May 30, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Han-Wen Hu, Yung-Chun Li
  • Patent number: 11664061
    Abstract: A memory device according to some aspects of the inventive concepts includes a memory cell array including a plurality of banks, at least one Processing Element (PE) connected to at least one bank selected from the plurality of banks, and a control logic configured to control an active operation in which wordlines included in each of the plurality of banks is activated, and configured to control a refresh operation in which at least one bank is refreshed, based on a PE enable signal configured to selectively enable the at least one PE.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: May 30, 2023
    Inventors: Youngcheon Kwon, Sanghyuk Kwon, Kyomin Sohn, Jaeyoun Youn, Haesuk Lee
  • Patent number: 11657874
    Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: May 23, 2023
    Assignee: Kioxia Corporation
    Inventors: Sanad Bushnaq, Noriyasu Kumazaki, Masashi Yamaoka
  • Patent number: 11651800
    Abstract: A data storage includes a memory array including a plurality of memory cells, and peripheral circuitry disposed underneath the memory array. The peripheral circuitry includes an M-tier sense amplifier (SA) circuit including X stacks of SA latches, wherein each SA latch is respectively coupled to a bit line of a memory cell of the plurality of memory cells; and an N-tier memory cache data (XDL) circuit including Y stacks of XDL latches, wherein M is less than N, and X is greater than Y. The peripheral circuitry further includes data path circuitry coupling (i) each SA latch of the X stacks of SA latches to (ii) a respective XDL latch of the Y stacks of XDL latches.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: May 16, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Feng Lu, Jongyeon Kim, Ohwon Kwon
  • Patent number: 11651832
    Abstract: A memory device includes: a normal cell region suitable for storing write data and outputting read data; a parity cell region suitable for storing write parity bits and outputting read parity bits; a pattern generation circuit suitable for generating test data whose value is sequentially increased, and providing the test data as the write data, in a first test mode; an error correction circuit suitable for generating the write parity bits based on the write data, correcting an error of the read data based on the read parity bits, and outputting the error-corrected data; and an output circuit suitable for compressing the error-corrected data and outputting the compressed data, wherein the output circuit is further suitable for compressing the read parity bits output from the parity cell region to output the compressed data, in the first test mode.
    Type: Grant
    Filed: January 12, 2021
    Date of Patent: May 16, 2023
    Assignee: SK hynix Inc.
    Inventors: Hong Ki Moon, Seung Woo Lee, Dong Hee Han
  • Patent number: 11646066
    Abstract: A memory controller includes a command processor. When an access command is performed by the memory controller, the command processor generates a row address information to the memory before issuing an active command to the memory. The row address information and the active command are issued by the command processor based on the access command.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 9, 2023
    Assignee: Etron Technology, Inc.
    Inventor: Chun Shiah
  • Patent number: 11646064
    Abstract: Provided are a page buffer and a memory device including the same. A memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit including page buffer units in a first horizontal direction, the page buffer units being connected to the memory cells via bit lines, and cache latches in the first horizontal direction, the cache latches corresponding to the page buffer units, wherein each of the page buffer units includes one or more pass transistors connected to a sensing node of each of the plurality of page buffer units, the sensing node electrically connected to a corresponding bit line. Each sensing node included in each of the page buffer units and the combined sensing node are electrically connected to each other through the pass transistors.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongsung Cho, Inho Kang, Taehyo Kim, Jeunghwan Park, Jinwoo Park
  • Patent number: 11646067
    Abstract: A data storage device includes a nonvolatile memory device and a controller including a command parser configured to match a clock corresponding to each of a plurality of memory access types to generate a clock index matched with each of the memory access types and configured to determine, when a command is received, a memory access type of the command and the clock index matched with the determined memory access type by analyzing the command, and a memory interface configured to determine a locking value and the clock index corresponding to each of a plurality of clocks having different frequencies and change the locking value for processing of a command according to the clock index determined by the command parser.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: May 9, 2023
    Assignee: SK hynix Inc.
    Inventor: Dae Geun Jee
  • Patent number: 11631441
    Abstract: A memory device supporting multi-address read operations improves throughput on a bi-directional serial port. The device includes a memory array and an input/output port having an input mode and an output mode. The input/output port has at least one signal line used alternately in both the input and output modes. A controller includes logic configured to execute a multi-address read operation in response to receiving a read command on the input/output port, the multi-address read operation including receiving a first address and a second address using the at least one signal line before outputting data.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: April 18, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Kuen-Long Chang, Su-Chueh Lo, Yung-Feng Lin
  • Patent number: 11626185
    Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun Kim, Yoon-Na Oh, Hyung-Jin Kim, Hui-Kap Yang, Jang-Woo Ryu
  • Patent number: 11626171
    Abstract: A method of programming a nonvolatile memory device includes performing a single-pulse program operation in a program loop, determining whether a condition is satisfied in the a program loop, and performing a multi-pulse program operation in a next program loop when the condition is satisfied. The single-pulse program operation includes applying a first program pulse and applying plural verification pulses, the multi-pulse program operation includes applying a second program pulse, applying a third program pulse, and applying plural verification pulses, and each of the second program pulse and the third program pulse has a level lower than a level of the first program pulse.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joonsuc Jang, Hyunggon Kim, Sangbum Yun, Dongwook Kim, Kyungsoo Park, Sejin Baek
  • Patent number: 11626177
    Abstract: An anti-fuse sensing device and an operation method thereof are provided. The anti-fuse sensing device is adapted for sensing a resistance state of an anti-fuse. The anti-fuse sensing device includes a voltage generating circuit, a comparison circuit, and a sensing circuit. The voltage generating circuit is configured to generate a comparison voltage that changes with temperature. The comparison circuit is coupled to the voltage generating circuit to receive the comparison voltage. The comparison circuit is configured to compare the comparison voltage with a reference voltage, and convert a difference between the comparison voltage and the reference voltage into a bias voltage that changes with temperature. The sensing circuit is coupled to the comparison circuit to receive the bias voltage. The sensing circuit is configured to sense the resistance state of the anti-fuse according to the bias voltage.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 11, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Hang Chang