Patents Examined by Muna A Techane
  • Patent number: 10998030
    Abstract: An integrated circuit memory contains a memory cell connected to a bit line that does not float during a portion or all of the read sensing part of the read cycle. The memory cell includes a data storage device. The data storage device may be a ferroelectric capacitor, a linear capacitor, a floating gate transistor, a magnetic device, a resistive device or other type of data storage device capable of placing a charge on the bit line corresponding to a specific data state of the memory cell. The bit line and a reference bit line are connected to a differential amplifier and precharged to specified voltages. Preferably, a self-nulling sense amplifier circuit is connected to the bit lines that compensates for sense amplifier offset by applying additional charges on the bit lines. Alternatively, charge sources may be connected to the bit lines to provide additional charges on the bit lines during the read cycle.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: May 4, 2021
    Inventors: Daryl G Dietrich, Gary F Derbenwick
  • Patent number: 10991403
    Abstract: A method and apparatus for performing memory calibration with endpoint replay is disclosed. A first calibration of a data strobe signal in a memory subsystem is performed. The first calibration includes determining initial values of first and second endpoints indicative of first and second delay values, respectively, applied to the data strobe signal. A second calibration of the data strobe signal is performed around these endpoints, within a range thereof that is less than a full range there between. Based on the second calibration, the endpoints are adjusted.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: April 27, 2021
    Assignee: Apple Inc.
    Inventors: Robert E. Jeter, Rakesh L. Notani, Venkata R. Malladi
  • Patent number: 10984858
    Abstract: A semiconductor storage device includes: a voltage generation circuit configured to generate a read voltage to be supplied to a selected word line to which a read-target memory cell transistor is connected and a read-pass voltage to be supplied to an adjacent word line; a word line driver configured to, when the read voltage transitions, apply the read voltage to the selected word line with a first kick voltage amount and apply the read-pass voltage to the adjacent word line with a second kick voltage amount; and a control circuit configured to set each of the first kick voltage amount and the second kick voltage amount to a voltage corresponding to an amount of the transition.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: April 20, 2021
    Assignee: Kioxia Corporation
    Inventor: Hiroki Date
  • Patent number: 10976943
    Abstract: The present disclosure includes apparatuses and methods to change data category values. An example is a memory device that includes an array having a plurality of sequences of memory cells, where each of the respective sequences of memory cells includes a plurality of designated subsets of memory cells, and the array includes a counter corresponding to one of the plurality of designated subsets of memory cells. The memory device is configured to receive input corresponding to a data batch, where the input includes a designation that corresponds to the one of the plurality of designated subsets of memory cells to be conditionally updated, and to change a numerical value stored by the counter corresponding to the one of the plurality of designated subsets of memory cells.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Jeremiah J. Willcock
  • Patent number: 10971217
    Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Yen-Huei Chen, Mahmut Sinangil
  • Patent number: 10971247
    Abstract: A method includes replacing an address of a first normal memory cell in a first column of a first memory block with a destination address that is an address of a second normal memory cell in a second column of the first memory block, and reassigning the address of the second normal memory cell in the second column of the first memory block to an address of a first redundancy memory cell in a redundancy block of the memory device.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-Ryun Kim, Yoon-Na Oh, Hyung-Jin Kim, Hui-Kap Yang, Jang-Woo Ryu
  • Patent number: 10957401
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: March 23, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
  • Patent number: 10950288
    Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Bill Nale, Christopher E. Cox
  • Patent number: 10950614
    Abstract: A single poly non-volatile memory device that includes: a first type lower well; first and second wells separately formed in an upper portion of the first type lower well; a source electrode, a selection transistor, a sensing transistor, and a drain electrode sequentially disposed in an upper portion of the first well. A control gate is formed in an upper portion of the second well with separated on an opposite side of the source electrode from the first well and connected to the gate of the sensing transistor.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: March 16, 2021
    Assignee: Key Foundry Co., Ltd.
    Inventors: Su Jin Kim, Hye Jin Yoo
  • Patent number: 10950311
    Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 16, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Kiyohiko Sakakibara, Ippei Yasuda, Ken Oowada, Masaaki Higashitani
  • Patent number: 10937494
    Abstract: Briefly, the disclosure relates to circuits utilized to perform writing operations to a memory array, in which elements of the array comprise resistive memory cells coupled in series with an access device. In one embodiment, a circuit may comprise a supply voltage coupled to a first side of the array and a current source coupled to a second side of the array. The access devices of the elements of the array may be body-biased, which may operate to reduce the turn-on voltage (VTH) of the access devices. Particular voltages may be applied to gate regions of the access devices to control leakage current to the resistive memory cells of the array.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 2, 2021
    Assignee: Arm Limited
    Inventors: El Mehdi Boujamaa, Akshay Kumar
  • Patent number: 10937512
    Abstract: A method of managing programming errors in a multilevel NAND flash memory is provided. The multilevel NAND flash memory uses a two-pass programming algorithm—e.g., a first programming pass and a second programming pass—for programming a memory block being organized in pages, sharing a word line. The method comprises performing the first programming pass for at least one memory page, reading the at least one memory page between the first programming pass and the second programming pass, determining an error count value for the at least one programmed memory page, and responsive to determining that the error count value is below a threshold value, performing the second programming pass with active data.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolaos Papandreou, Thomas Mittelholzer, Roman Alexander Pletka
  • Patent number: 10937510
    Abstract: A method for identifying cell coupling in a memory system includes generating a two-dimensional pseudorandom binary sequence array. The method also includes performing an erase operation on a plurality of cells of a memory block of the memory system. The method also includes performing a write operation on the plurality of cells using the two-dimensional pseudorandom binary sequence array. The method also includes performing a read operation on the plurality of cells to identify a voltage value for each cell of the plurality of cells. The method also includes identifying cell coupling between respective cells of the plurality of cells using the voltage value for each of the cells of the plurality of cells.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: March 2, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard Galbraith, Jonas Goode, Henry Yip, Ravi Kumar, Niranjay Ravindran
  • Patent number: 10923181
    Abstract: The semiconductor memory device including a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal, a data input buffer configured to receive data delayed by a first delay time compared to the data strobe signal and generate input data, a latency control signal generator configured to generate and activate a first on-die termination control signal during a first period in which the data strobe signal is applied in response to receiving a write command, a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal, and a data strobe signal termination circuit configured to terminate the data strobe signal and including a first on-die termination resistor, a resistance value of which varies in response to the first variable resistance code may be provided.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Ju Ho Jeon, Hun-Dae Choi
  • Patent number: 10923190
    Abstract: According to one embodiment, a device includes: a memory cell between the first and second interconnects; a first circuit in a domain having a range of a first voltage to a second voltage higher than the first voltage, the first circuit controlling supply of the second voltage to the first interconnect; a second circuit in a domain having a range of a third voltage lower than the first voltage to the first voltage, the second circuit controlling supply of the third voltage to the second interconnect; and a third circuit in a domain having a range of a fourth voltage lower than the first voltage to a fifth voltage higher than the first voltage, the third circuit controlling supply of a sixth voltage to the first and second interconnects.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: February 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Yutaka Shirai
  • Patent number: 10923189
    Abstract: According to one embodiment, a memory device includes a memory cell including a resistance change memory element and a selector element, a word line, a bit line connected to one end of the memory cell, an operational amplifier including a non-inverting input connected to the bit line, an output circuit including a first terminal connected to an output of the operational amplifier, a second terminal connected to the bit line, and a charge/discharge circuit including a capacitor, a charge circuit and a discharge circuit, each including one end connected to an inverting input of the operational amplifier. At the time of falling of a write voltage for the memory cell, a potential of the other end of the memory cell is set higher than a potential of the other end of the discharge circuit.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: February 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryu Ogiwara, Daisaburo Takashima, Takahiko Iizuka
  • Patent number: 10923161
    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitcell and multiple straps including a first strap, a second strap, and a third strap. The first strap may couple the bitcell to ground. The second strap may couple the bitcell to a bitline. The third strap may couple the bitcell to a wordline within a boundary of the bitcell.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: February 16, 2021
    Assignee: Arm Limited
    Inventors: Sumant Kumar Thapliyal, Sumeet Sawant, Avinash Merugu, Deeksha Anandani, Veera Raghavulu Marella, Srinath Gopinath, Abdullah Shahid
  • Patent number: 10910021
    Abstract: Disclosed is a semiconductor device in which an internal voltage fluctuation when a current jump occurs is restrained. The semiconductor device includes a plurality of blocks, each of which performs a given operation, and a current jump control circuit. The current jump control circuit monitors control signals in each of the blocks and calculates predicted values of consumption current of the blocks, based on results of monitoring at different timings, thereby controlling a fluctuation of consumption current of the blocks. The current jump control circuit controls operation of a subset or all of the blocks, if an increase of a predicted value of consumption current of the blocks is larger than a first value or a decrease of the predicted value is larger than a second value.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Naoshi Ishikawa
  • Patent number: 10910079
    Abstract: A programming device (110) arranged to obtain and store a random bit string in a memory device (100), the memory device (100) comprising multiple one-time programmable memory cells (122), a memory cell having a programmed state and a not-programmed state, the memory cell being one-time programmable by changing the state from the not-programmed state to the programmed state through application of an electric programming energy to the memory cell.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: February 2, 2021
    Assignee: INTRINSIC ID B.V.
    Inventors: Pim Theo Tuyls, Geert Jan Schrijen, Vincent Van Der Leest
  • Patent number: 10910544
    Abstract: Superconducting circuits and memories that use a magnetic Josephson junction (MJJ) device as a pi inverter are disclosed. The MJJ device includes superconducting layers configured to allow a flow of a supercurrent through the MJJ device. The MJJ device further includes a magnetic layer arranged between the superconducting layers, where the magnetic layer has an associated magnetization direction, and where the first state of the MJJ device corresponds to a zero-phase of a supercurrent flowing through the MJJ device and the second state of the MJJ device corresponds to a ?-phase of the supercurrent flowing through the MJJ device. In response to an application of a magnetic field, without any change in the magnetization direction of the magnetic layer, the MJJ device is configured to switch from the first state to the second state responsive to a change in a phase of the supercurrent.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: February 2, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Thomas F. Ambrose, James M. Murduck