Abstract: A row decoder circuit includes an input node receiving a row selection signal and an output node coupled to a memory device word line. A pull-down circuit couples the word line to ground in response to the row selection signal being asserted. A pull-up circuit couples the word line to a supply node in response to a deselection signal being de-asserted. An inverter circuit receives as input a control signal from a control node and produces the deselection signal. A current generator sources a biasing current to the control node. A further pull-down circuit couples the control node to ground in response to the row selection signal being asserted, and comprises a first cascode n-channel transistor, a cascode p-channel transistor, a second cascode n-channel transistor, and at least one selection transistor controlled by the row selection signal, all having their conductive channels arranged in series.

Abstract: Embodiments of the present disclosure relate to a storage device based on a daisy chain topology. According to embodiments of the present disclosure, a storage device may include a plurality of memory package chips each including a plurality of memory dies capable of storing data; and a controller communicating with the plurality of memory package chips and connected to the plurality of memory package chips through one or more daisy chain circuits.

Abstract: A memory apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means is configured to erase the memory cells in an erase operation. The control means is also configured to apply each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the data states to selected ones of the word lines to program and verify the memory cells connected thereto during a program operation. At least one of the plurality of program verify voltages is adjusted for the memory cells connected to one or more defective ones of the word lines in response to an erase verify of the erase operation failing for the memory cells connected to the one or more defective ones of the word lines.

Abstract: A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body transistor are electrically connected in series through a common node. The first floating body transistor and the second floating body transistor store complementary data.

Abstract: A memory device is disclosed. The memory device includes a memory array comprising a plurality of memory cells. At least a first one of the memory cells, by default, permanently presents a first logic state based on a short circuit. At least a second one of the memory cells, by default, permanently presents a second logic state opposite to the first logic state based on an open circuit.

Abstract: An aspect of the present disclosure is a semiconductor device including: a property-variable element, an electrical property thereof changes with application of a higher voltage than a predetermined voltage; a write control switch that switches between conductive and non-conductive states based on a first signal; a first circuit that outputs a write voltage based on a power source and a second signal, the electrical property of the element being changed due to the application of the higher voltage to the element when the write voltage is output from the first circuit and the switch is in the conductive state; wiring for applying the higher voltage to the element; a second circuit that detects noise at the power source; and a noise discharge switch that enables noise current to be discharged from the wiring when the second circuit detects noise at the power source.

Abstract: A semiconductor device is provided. The semiconductor device includes: a memory cell array including a plurality of memories arranged on a plurality of rows and a plurality of columns, each of the memories being a volatile memory; a plurality of repair circuits configured to repair the memory cell array; a selection circuit configured to select, from the plurality of repair circuits, a repair circuit to be connected to a memory included in the plurality of memories; and a holding circuit configured to hold selection information for selecting, by the selection circuit, a designated repair circuit out of the plurality of repair circuits, and control the selection circuit based on the selection information. The selection circuit is configured to be able to select at least two repair circuits in parallel out of the plurality of repair circuits.

Abstract: Provided is a magnetoresistive element with a second magnetic layer. The second magnetic layer is a perpendicular magnetization layer when no voltage is applied to the magnetoresistive element, changes from the perpendicular magnetization layer to an in-plane magnetization layer when a first voltage is applied to the magnetoresistive element, and changes from the perpendicular magnetization layer to the in-plane magnetization layer when a second voltage is applied to the magnetoresistive element. Magnetization of the second magnetic layer changes to a first direction of a direction perpendicular to a plane of the layer after a third voltage is applied to the magnetoresistive element for a first period of time and changes to a second direction of the direction perpendicular to the plane of the layer after a fourth voltage is applied to the magnetoresistive element for a second period of time.

Abstract: An automated device and method for erasing data stored in non-volatile memories of electronic devices, such as smartphones or tablets, is disclosed. The device includes the use of an irradiation chamber having at least one X-ray source confined in a X-ray-tight enclosure, capable of receiving a plurality of electronic devices that can be brought into the chamber by a conveyor. A control unit controls the conveyor and the X-ray source to irradiate each electronic device with controlled power and duration for erasing data stored in the non-volatile memories of the electronic devices.

Abstract: An erasable programmable non-volatile memory cell includes an isolation structure, a first P-well region, a second P-well region, an N-type isolation region, a first gate structure, a second gate structure, a first merged doped region, a second merged doped region, a third merged doped region and a fourth merged doped region. The isolation structure is formed on a P-type semiconductor substrate. The first gate structure and the second gate structure are formed on the surface of the P-type semiconductor substrate corresponding to the first region. An area the P-type semiconductor substrate corresponding to the first region are divided into a first merged doped region, a second merged doped region and a third merged doped region. The fourth merged doped region is formed in the P-type semiconductor substrate corresponding to the second region.

Abstract: A memory includes a read/write amplifier configured to retrieve read data from a memory array, and a neural network based preconditioning circuit configured to receive a read data signal according to the read data. A neural network of the preconditioning circuit is configured to precondition the read data signal based on a characteristic of a read data transmission path to provide a modified read data signal. The memory further includes an output driver configured to transmit the modified read data signal.

Abstract: A low-power programmable erasable nonvolatile memory includes common-source lines, word lines, bit lines, memory arrays, a first electronic switch, a second electronic switch, a decoding device, a first storage capacitor, a second storage capacitor, and a voltage boosting circuit. Each memory array is coupled to one common-source line, one word line, and four bit lines. The decoding device is coupled to the common-source lines, the word lines, the bit lines, a high voltage, a middle voltage, a low voltage, and a grounding voltage. One end of the storage capacitor is coupled to a reference voltage and another end of the storage capacitor is coupled to the decoding device through the electronic switch. The voltage boosting circuit, coupled to the first storage capacitor, charges the first storage capacitor to perform a programming activity or an erasing activity.

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a memory cell array, a memory interface, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit supports a first memory protocol, and the second peripheral circuit supports a second memory protocol different from the first memory protocol. The first peripheral circuit and the second peripheral circuit share the memory cell array and the memory interface.

Abstract: In some aspects of the present disclosure, a memory circuit is disclosed. In some aspects, the memory circuit includes a first storage element coupled to a first bit line, a first transistor coupled between the first storage element and a center node, a second storage element coupled to a second bit line, a second transistor coupled between the second storage element and the center node, and a third transistor coupled between the center node and a reference node.

Abstract: Apparatuses, systems, and methods for access based targeted refresh operations. A memory bank has a first sub-bank and a second sub-bank. A refresh control circuit detects an aggressor in one of the sub-banks. Responsive to an access in the other sub-bank, the refresh control circuit performs a targeted refresh operation based on the sub-bank based on the aggressor address.

Abstract: A power supply apparatus includes: a power supply terminal receiving a first voltage from outside; one or more step-down circuits each generating a second voltage to be supplied to a memory device; first and second coupling lines disposed parallel to each other and individually coupling the power supply terminal and the step-down circuit(s) to each other; a first switching device disposed on the first coupling line, between the power supply terminal and the step-down circuit(s); a step-up circuit disposed on the second coupling line and stepping up the first voltage supplied from the power supply terminal; a first capacitor disposed on the second coupling line, between the step-up circuit and the step-down circuit(s); a second switching device disposed on the second coupling line, between the step-up circuit(s) and the first capacitor, and a third switching device disposed on the second coupling line, between the first capacitor and the step-down circuit(s).

Abstract: A memory device includes control circuitry that executes a first programming operation and executes a second programming operation after the first programming operation. The first programming operation includes setting a threshold voltage of each of a second set of memory cells in a second section corresponding to write data, and setting a threshold voltage of each of the third set of memory cells in a third section. The second programming operation includes setting the threshold voltage of each of the second set of memory cells in a fifth section corresponding to the write data, and setting the threshold voltage of each of the third set of memory cells in a sixth section or a seventh section among a plurality of fourth sections in accordance with temperature information. The sixth section includes the same voltage range as the third section. The seventh section is higher in voltage than the third section.

Abstract: A memory device including a plurality of memory dies positioned in a stack, the plurality of memory dies including a first set of memory dies having a first number of channels configured according to a first configuration and a second number of channels configured according to a second configuration, wherein the first configuration comprises channels configured to have a first bandwidth and operate in a first bandwidth mode, and the second configuration comprises channels configured to have a second bandwidth and operate in a second bandwidth mode, and a second set of memory dies having a third number of channels configured according to the first configuration and a fourth number of channels configured according to the second configuration, wherein the first bandwidth is larger than the second bandwidth, the first number is larger than the third number, and the second number is larger than the fourth number.

Abstract: A method of programming a memory cell to a target program state associated with a target read current, comprising applying a first pulse of programming voltages that includes a first control gate voltage, applying a second pulse of programming voltages that includes a second control gate voltage, performing a read operation that includes detecting currents through the memory cell for different voltages applied to the control gate, determining a first read voltage for the control gate using the detected currents that corresponds to the target read current, determining a target programming voltage using the second voltage, the first read voltage, a control gate nominal read voltage and a tuning factor, erasing the memory cell, applying a third pulse of programming voltages that includes the first control gate voltage, and applying a fourth pulse of programming voltages that includes the target programming voltage applied to the control gate.

Abstract: A method and device for erasing a memory cell with a floating gate, by applying successive first erase pulses to the memory cell to remove electrons from the floating gate until a coarse target read current, and then applying successive second erase pulses to the memory cell to remove electrons from the floating gate until a target read current for the memory cell is achieved. The first erase pulses include a first parameter following a first progression that changes in value after respective ones of the first erase pulses. The first progression begins with a first value and ends with a second value. The second erase pulses include the first parameter following a second progression in which the first parameter changes in value after respective ones of the second erase pulses. The second progression begins with a third value that is between, and unequal to, the first and second values.