Abstract: A power supply apparatus includes: a power supply terminal receiving a first voltage from outside; one or more step-down circuits each generating a second voltage to be supplied to a memory device; first and second coupling lines disposed parallel to each other and individually coupling the power supply terminal and the step-down circuit(s) to each other; a first switching device disposed on the first coupling line, between the power supply terminal and the step-down circuit(s); a step-up circuit disposed on the second coupling line and stepping up the first voltage supplied from the power supply terminal; a first capacitor disposed on the second coupling line, between the step-up circuit and the step-down circuit(s); a second switching device disposed on the second coupling line, between the step-up circuit(s) and the first capacitor, and a third switching device disposed on the second coupling line, between the first capacitor and the step-down circuit(s).

Abstract: A memory device includes control circuitry that executes a first programming operation and executes a second programming operation after the first programming operation. The first programming operation includes setting a threshold voltage of each of a second set of memory cells in a second section corresponding to write data, and setting a threshold voltage of each of the third set of memory cells in a third section. The second programming operation includes setting the threshold voltage of each of the second set of memory cells in a fifth section corresponding to the write data, and setting the threshold voltage of each of the third set of memory cells in a sixth section or a seventh section among a plurality of fourth sections in accordance with temperature information. The sixth section includes the same voltage range as the third section. The seventh section is higher in voltage than the third section.

Abstract: A method of programming a memory cell to a target program state associated with a target read current, comprising applying a first pulse of programming voltages that includes a first control gate voltage, applying a second pulse of programming voltages that includes a second control gate voltage, performing a read operation that includes detecting currents through the memory cell for different voltages applied to the control gate, determining a first read voltage for the control gate using the detected currents that corresponds to the target read current, determining a target programming voltage using the second voltage, the first read voltage, a control gate nominal read voltage and a tuning factor, erasing the memory cell, applying a third pulse of programming voltages that includes the first control gate voltage, and applying a fourth pulse of programming voltages that includes the target programming voltage applied to the control gate.

Abstract: A memory device including a plurality of memory dies positioned in a stack, the plurality of memory dies including a first set of memory dies having a first number of channels configured according to a first configuration and a second number of channels configured according to a second configuration, wherein the first configuration comprises channels configured to have a first bandwidth and operate in a first bandwidth mode, and the second configuration comprises channels configured to have a second bandwidth and operate in a second bandwidth mode, and a second set of memory dies having a third number of channels configured according to the first configuration and a fourth number of channels configured according to the second configuration, wherein the first bandwidth is larger than the second bandwidth, the first number is larger than the third number, and the second number is larger than the fourth number.

Abstract: A method and device for erasing a memory cell with a floating gate, by applying successive first erase pulses to the memory cell to remove electrons from the floating gate until a coarse target read current, and then applying successive second erase pulses to the memory cell to remove electrons from the floating gate until a target read current for the memory cell is achieved. The first erase pulses include a first parameter following a first progression that changes in value after respective ones of the first erase pulses. The first progression begins with a first value and ends with a second value. The second erase pulses include the first parameter following a second progression in which the first parameter changes in value after respective ones of the second erase pulses. The second progression begins with a third value that is between, and unequal to, the first and second values.

Abstract: To reduce power consumption and circuitry requirements, the following presents an “unmatched” data output architecture, in which the clock path does not mimic the data path. To provide proper data transfers in the data output path, the clock signal is tuned at points of the clock path, such as for data transfers from internal data buses to FIFOs and from the FIFO though the multiplexers to the input/output pads. An amount of timing offset is introduced in the generation of internal transfer clocks, which can be determined as part of a valid data window training process that can be performed by the controller, such as part of the power up process. To more quickly train the memory dies and determine the timing offset for an unmatched data output architecture, replica circuits for the data path and the clock path can be introduced on to the memory dies.

Abstract: The present technology relates to a memory system. A memory device according to the present technology may include a memory cell array including memory cells connected to a plurality of word lines, a peripheral circuit configured to apply operation voltages to the plurality of word lines during a voltage increase period in which a program voltage is applied to a select word line, selected among the plurality of word lines, until a voltage level of the select word line reaches a target level, and a control logic configured to control the peripheral circuit to apply a step-up voltage to adjacent word lines, adjacent to the select word line, after a predetermined time from the application of the program voltage and apply a step-down voltage to the adjacent word lines before an end of the voltage increase period, and the operation voltages include the program voltage, the step-up voltage, and the step-down voltage.

Abstract: Systems, methods, and apparatus related to unity buffers in memory devices. In one approach, a memory device includes memory arrays having memory cells. The memory device includes access lines to access the memory cells. The memory device includes unity buffers to drive the access line loads. Each buffer has an output current limiter that limits current flow when driving a voltage on the access lines. By limiting the current, the current limiter provides improved frequency response and operating stability for the buffer without the need for a compensation net.

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: Some embodiments of the disclosure provide an apparatus comprising: a word line array including a plurality of word lines each extending through a memory mat in a first horizontal direction, the plurality of word lines including first and second word lines arranged adjacent to each other in a second horizontal direction; and a word line contact of the first word line, the word line contact separated from the second word line by a gap. The first and second word lines each have a first oxide film at a center area of the word line array in the memory mat. The first and second word lines each have a second oxide film at an edge area of the word line array outside the memory mat, the second oxide film having a thickness greater than a thickness of the first oxide film.

Abstract: An FDSOI transistor control device includes a plurality of first wells having a first type of conductivity, each first well being associated with a group of transistors, and at least one second well having a second type of conductivity, formed under and around the first wells (21). A bias circuit is configured to apply at least one first bias voltage to the first wells and at least one second bias voltage to at least one second well. All of the transistors may have the second type of conductivity.

Abstract: A memory test is proposed wherein a majority of the address lines are switched on every cycle. Increasing a number of switched address lines increases an ability to detect cross coupling problems between address lines and maximizes power usage to detect power issues. In one example, on every even cycle, the address lines use a first incrementing or decrementing pattern, while every odd cycle, the address lines use a second incrementing or decrementing pattern. The first pattern can be an opposite direction of counting than the second pattern, such that if one is incrementing, the other is decrementing or vice versa. The first and/or second pattern can be binary, Gray code, or other patterns.

Abstract: A semiconductor apparatus includes a power gating control circuit and a power gating circuit. The power gating control circuit generates a power gating signal based on an idle signal, a clock synchronization signal, and a delayed idle signal. The power gating circuit applies at least a first operating voltage to an internal circuit based on the power gating signal.

Abstract: A semiconductor integrated circuit includes: a power supply pin configured to receive an external power supply voltage; a fuse memory circuit including a fuse element; and a power supply circuit, whose output is connected to the fuse memory circuit, configured to receive the external power supply voltage, the power supply circuit being switchable in response to a control signal between (i) a first state in which an internal power supply voltage of a first voltage level, which is capable of cutting the fuse element, is supplied to a power supply line of the fuse memory circuit and (ii) a second state in which the internal power supply voltage of a second voltage level lower than the first voltage level, which is incapable of cutting the fuse element, is supplied to the power supply line of the fuse memory circuit.

Abstract: Apparatuses, systems, and methods for separate write enable signals for data, metadata, and parity information. A memory array is divided into column planes and an extra column plane. In some modes of the memory device, data and parity information is stored in the column planes and metadata is stored in the extra column plane. The extra column plane includes separate write enable signals (or separate states of a single signal) which activate different portions of the bit lines (e.g., even and odd bit lines). In an example access operation, a column select signal is provided to the extra column plane along with one or the other write enable signals such that fewer than all of the bit lines activated by the column select signal provide data.

Abstract: Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.

Abstract: A storage device is disclosed. The storage device is configured to: determine data states for a first set of memory cells of a first neighboring word line of the and a second set of memory cells of a second neighboring word line, the first and the second neighboring word lines being adjacent to a selected word line; identify a zone of a plurality of zones for each data state combination of the data states, each data state combination comprising a data state of a memory cell of the first set of memory cells and a data state of a memory cell of the second set of memory cells, each zone of the plurality of zones corresponding to a bit line clamping voltage; and perform a read operation on the selected word line including applying each bit line clamping voltage corresponding to any zones identified.

Abstract: A memory apparatus and operating method are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is configured to apply a pre-programming pulse of a pre-program voltage to a selected one and at least one neighboring one of the plurality of word lines in a pre-program operation. The control means is also configured to apply each of a series of programming pulses of a program voltage followed by verification pulses of a plurality of program verify voltages each associated with one of the plurality of data states to the selected one of the plurality of word lines to program and verify the memory cells connected thereto during each of a plurality of program loops of a program operation.

Abstract: A semiconductor device includes a memory cell including a first transistor, a second transistor, and a resistor. Each of the first transistor and the second transistor is operatively coupled to the resistor in series. The second transistor is formed below the resistor such that the second transistor provides heat to the resistor when the memory cell is being programmed.

Abstract: A semiconductor memory device includes memory cell transistors and a control circuit. The control circuit is configured to set a threshold voltage of each memory cell transistor to be in one of voltage ranges to store multi-bit data in each memory cell transistor. The voltage ranges include a first range corresponding to a first multi-bit value, a second range lower than the first range and corresponding to a second multi-bit value, and a third range that is the lowest. When a target memory cell transistor in which data of the second multi-bit value is to be written currently stores data of the first multi-bit value, the control circuit is configured to apply a first voltage to a gate of the target memory cell transistor, to shift the threshold voltage of the target memory cell transistor to be in the second range without dropping into the third range.