Patents Examined by Mushfique Siddique
  • Patent number: 10997498
    Abstract: The present disclosure relates to a structure including a differential memory array circuit which is configured to perform a binary convolution of two input word operands by accumulating a summation of currents through a plurality of bits which are each arranged between a wordline and a sourceline in a horizontal direction and bitlines in a vertical direction.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 4, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Amogh Agrawal, Ajey Poovannummoottil Jacob
  • Patent number: 10998053
    Abstract: A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 4, 2021
    Assignee: SK hynix Inc.
    Inventors: Jung Hwan Lee, Jung Mi Ko, Ji Hwan Kim, Kwang Ho Baek, Young Don Jung
  • Patent number: 10998440
    Abstract: A device comprises a vertical transistor. The vertical transistor comprises a semiconductive pillar, at least one gate electrode, a gate dielectric material, and void spaces. The semiconductive pillar comprises a source region, a drain region, and a channel region extending vertically between the source region and the drain region, the channel region comprising a semiconductive material having a band gap greater than 1.65 electronvolts. The at least one gate electrode laterally neighbors the semiconductive pillar. The gate dielectric material is laterally between the semiconductive pillar and the at least one gate electrode. The void spaces are vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related electronic systems and methods are also disclosed.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Ramanathan Gandhi, Hong Li, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Sanh D. Tang, Scott E. Sills
  • Patent number: 10991441
    Abstract: A flash device endurance test method is provided. A flash device to be tested, which has a plurality of memory cells, includes multiple ports with the same and different test conditions. The method includes connecting the ports of the same test condition to the same pulse generation unit, and connecting the ports of different test conditions to different pulse generation units; generating by all of the pulse generation units, synchronous pulse voltage signals of N cycles, wherein one time of erasing-writing of the flash device is considered to be one of the cycles; and testing threshold voltages of erasing and writing states in each cycle.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 27, 2021
    Assignee: Shanghai Huali Microelectronics Corporation
    Inventor: Hongliang Du
  • Patent number: 10984843
    Abstract: A memory cell arrangement for Random Access Memory (RAM) including one or more RAM cell groups. The RAM cell groups having two or more local bit-lines sharing a Global Bit-Line (GBL), a pre-charging circuit connected to the GBL, a multiplexer connected to multiple GBLs and configured to shift an output of a first GBL from a first bit to a second bit at least in part according to a value of a fuse bit register associated with a second GBL, and at least one pre-charge enabling circuit controlled by a combination of a pre-charge input value applied to all GBLs of the memory cell arrangement and a pre-charge enable signal for the GBL.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Martin Bernhard Schmidt, Harry Barowski, Simon Brandl, Wolfgang Penth
  • Patent number: 10978111
    Abstract: In an aspect of the disclosure, a reference voltage holding circuit is provided. The reference voltage holding circuit is for maintaining a sense amplifier reference voltage provided by a sense amplifier reference circuit, and the reference voltage holding circuit includes: a reference voltage generating circuit configured to provide a bias reference voltage; a current generating circuit electrically coupled to the reference voltage generating circuit and configured to receive the bias reference voltage to output a standby bias voltage and a standby bias current; and a voltage pull-up circuit electrically coupled to the current mirror circuit and configured to provide for the standby bias current and to maintain the standby bias voltage which drives the sense amplifier reference voltage when reference voltage holding circuit operates under a standby operation and approximates the sense amplifier reference voltage as long as the sense amplifier reference voltage remains enabled.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: April 13, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Poongyeub Lee, Ting-Kuo Yen
  • Patent number: 10978147
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a bit line, a word line crossing the bit line, and a memory cell coupled to and disposed between the bit line and the word line. In a read operation, when the word line, which is in a precharged state, is floated, the bit line is driven to increase a voltage level of the bit line, and stopped when the memory cell is turned on.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyung Dong Lee, Tae Hoon Kim
  • Patent number: 10971225
    Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: April 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kikuko Sugimae, Yusuke Arayashiki
  • Patent number: 10971245
    Abstract: A system and method for testing a magnetic memory cell in a bit cell array to determine whether the electrical resistance values of the memory cell are within acceptable parameters. The system and method allows for the determination of the electrical resistance of the memory cell without parasitic resistance associated with that memory cell in order to accurately determine the electrical resistance of the memory cell.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 6, 2021
    Assignee: SPIN MEMORY, INC.
    Inventor: Minh Quang Tran
  • Patent number: 10964373
    Abstract: A memory cell in capacitive logic, including a bistable system including a fixed element and a mobile element capable of taking one or the other of two stable positions with respect to the fixed element; a read device including a variable-capacitance capacitor including a first fixed electrode and a second mobile electrode rigidly fixed to the mobile element; and an electrically controllable write device for placing the mobile element in one or the other of its two stable positions.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 30, 2021
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Yann Perrin, Hervé Fanet, Ayrat Galisultanov, Gaël Pillonnet
  • Patent number: 10964378
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
  • Patent number: 10964368
    Abstract: According to one embodiment, a semiconductor memory device, includes a memory cell comprising a switching element and a resistance change element; and a first circuit that applies a first voltage to the memory cell, places the memory cell into an ON state by applying a second voltage to the memory cell while applying the first voltage to the memory cell in parallel, generates a third voltage based on a resistance state of the resistance change element by performing first voltage application to perform a first readout on the memory cell in the ON state, writes first data into the memory cell.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 30, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Ryousuke Takizawa
  • Patent number: 10957403
    Abstract: A semiconductor device includes a first current circuit, a first resistor, a second resistor, a second current circuit, and a third resistor. The first current circuit is configured to output a first current to a first node using a first voltage supplied thereto. The first resistor is connected to the first node. The second resistor has a first end connected to a second node that is at a same voltage level as the first node and a second end. The second current circuit is configured to output a second current to a third node using a second voltage, which is higher than the first voltage, supplied thereto. The third resistor is connected between the second end of the second resistor and the third node.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: March 23, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoko Deguchi, Masahiro Yoshihara, Yoshihiko Kamata, Takuyo Kodama
  • Patent number: 10950301
    Abstract: A two transistor, one resistor gain cell and a suitable storage element are described. In some embodiments the gain cell has a resistive memory element coupled to a common node at one end to store a value and to a source line at another end, the value being read as conductivity between the common node and the source line of the resistive memory element, a write transistor having a source coupled to a bit line, a gate coupled to a write line, and a drain coupled to the common node to write a value at the bit line to the resistive memory element upon setting the write line high, and a read transistor having a source coupled to a bit line read line and a gate coupled to the common node to read the value written to the resistive memory element as a value at the second transistor gate.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Rafael Rios, Abhishek Anil Sharma, Van H. Le, Gilbert William Dewey, Jack T. Kavalieros
  • Patent number: 10950295
    Abstract: According to one embodiment, a semiconductor memory includes a first bit line; a second bit line; a source line; a first memory cell electrically connected between the first bit line and the source line and including a first transistor and a first capacitor; a second memory cell electrically connected between the second bit line and the source line and including a second transistor and a second capacitor; a third transistor electrically connected to the source line; and a sense amplifier circuit including a first node electrically connected to the first bit line and a second node electrically connected to the second bit line.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: March 16, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Chika Tanaka, Keiji Ikeda
  • Patent number: 10943662
    Abstract: An apparatus includes non-volatile memory and a control circuit configured to program the non-volatile memory. The control circuit is configured to change a programming order. In one aspect, the control circuit changes the order in which word lines are programmed from one point in time to another. In one aspect, the control circuit uses one order for programming one set of word lines and a different order for a different set of word lines. The sets of word lines could be in different sub-blocks, memory blocks, or memory dies. Such programming order differences can improve performance of error recovery.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 9, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Linnen, Jayavel Pachamuthu, Kirubakaran Periyannan
  • Patent number: 10943657
    Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Karthik Sarpatwari, Fabio Pellizzer, Jessica Chen, Nevil Gajera
  • Patent number: 10943645
    Abstract: A semiconductor device is provided. The semiconductor includes a plurality of memory cells arranged in rows and columns. The device further includes a plurality of primary word lines, each being connected to a first plurality of memory cells arranged in a row and a plurality of bit line pairs, each being connected to a second plurality of memory cells arranged in a column. The device further includes a word line driver circuit operative to select a first primary word line of the plurality of primary word lines and charge the selected first primary word line from a first end and a secondary word line operative to charge the selected first primary word line from a second end.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: March 9, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventor: Hyunsung Hong
  • Patent number: 10943628
    Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Randon K. Richards, Dirgha Khatri
  • Patent number: 10936953
    Abstract: Provided herein are compositions, devices, systems and methods for generation and use of biomolecule-based information for storage. Further provided are devices-having addressable electrodes controlling polynucleotide synthesis (deprotection, extension, or cleavage, etc.) The compositions, devices, systems and methods described herein provide improved storage, density, and retrieval of biomolecule-based information.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 2, 2021
    Assignee: Twist Bioscience Corporation
    Inventors: Bill James Peck, Brian Wayne Bramlett