Abstract: The present technology includes: a current mirror configured to apply a test current that is generated by a test voltage to a selected word line, among a plurality of word lines, and to generate a copy current by copying the test current; a comparison circuit configured to compare at least one reference current with the copy current to generate a comparison result signal; and a test control circuit configured to perform a first noise control mode that charges unselected word lines, among the plurality of word lines, with electric charges, in response to a test mode signal and floats the unselected word lines.

Abstract: A memory circuit comprises a signal buffer, a plurality of switch circuits, a temperature sensor, a path-length-compensation circuit and at least one data latch. The signal buffer is configured to receive a strobe signal. The plurality of switch circuits are coupled to the signal buffer through a plurality of signal paths respectively, wherein the lengths of the plurality of signal paths are equal. The temperature sensor is coupled to the plurality of switch circuits and configured to conduct one of the plurality of switch circuits according to temperature of the memory circuit. The path-length-compensation circuit comprises a plurality of input terminals connected in series, which are configured to respectively receive outputs of the plurality of switch circuits. The at least one data latch is coupled to an output terminal of the path-length-compensation circuit and configured to store or output data according to output of the path-length-compensation circuit.

Abstract: A memory system may include: a non-volatile memory device, a volatile memory device suitable for defining, as cold data, data stored in a word line, on which a refresh operation is performed a number of times greater than a reference number among a plurality of word lines coupled to a volatile memory cell array, and evicting the cold data, and a controller suitable for controlling operations of the volatile memory device and the non-volatile memory device, and storing the evicted cold data into the non-volatile memory device.

Abstract: A first insulating layer 21 is disposed on a substrate 20. N+ layers 2 are separated from the insulating layer and in directions horizontal and vertical to the substrate. P layers 1 contact the n+ layers 2 and extend in the horizontal direction. N+ layers 3 contact the p layers 1. Gate insulating layers 4 cover the p layers 1 and part of the n+ layers 2 and 3. Second gate conductor layers 6 are electrically separated from a first gate conductor layer 5 contacting the gate insulating layers 4. A conductor layer 12 contacts the n+ layers 2. A conductor layer 13 contacts the n+ layers 3. A second insulating layer 22 contacts the first gate conductor layer 5, the n+ layers 2, and the conductor layer 12. A third insulating layer 23 contacts the second gate conductor layers 6, the n+ layers 3, and the conductor layer 13.

Abstract: A sense amplifier capable of performing a logical NOT operation is provided, which includes a sense circuit, configured to sense a first voltage of a bit line and a second voltage of an inverse bit line; a first transistor, coupled between a first terminal of the sense circuit and the bit line; a second transistor, coupled between a second terminal of the sense circuit and the inverse bit line; and a third transistor, coupled between the bit line and the inverse bit line. First and second memory cells are respectively controlled by first and second word lines, and connected to the bit line. When the sense amplifier is in an inverse writing state, the sense amplifier writes the second voltage to the second memory cell through a predetermined path. A first logical state of the first voltage is complementary to a second logical state of the second voltage.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory controller may include a training controller, a training data storage, and a machine learning processor. The training controller may perform training of correcting interface signals exchanged with a memory device, generate training data that is a result of the training, and output the training data as sample training data based on a comparison result of a training reference and the training data. The training data storage may store training history information including plural pieces of sample training data. The machine learning processor may update the training reference through machine learning based on the training history information.

Abstract: A memory array is disclosed. The memory array includes a plurality of memory cells disposed over a substrate. Each of the memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs. First four of the memory cells that are coupled to four consecutive ones of the word lines and to a first one of the bit line pairs are abutted to one another on the substrate along a single lateral direction.

Abstract: A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit coupled between the current control circuit and a ground. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. First terminals of the first transistors each is in connection with one of the bit lines. Second terminals of the first transistors each is in connection with the discharge enable circuit. Third terminals of the first transistors are in connection with a reference current generator of the current control circuit.

Abstract: A memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a plurality of word lines, a plurality of bit lines, and a plurality of storage elements. The control circuit includes an ECC circuit that detects and corrects a data error stored in the plurality of storage elements, acquires first data by reading data stored in the plurality of storage elements of a page connected to the same word line with a first read voltage, acquires second data obtained by correcting the first data when the first data can be corrected by the ECC circuit, and writes data based on the second data to the plurality of storage elements of the page.

Abstract: A control method to operate a memory device, a control method to operate a memory system and a control system are provided. The control method includes providing a first voltage to a memory device for accessing a memory element of the memory device; obtaining an aging information of the memory device; and providing a second voltage to the memory device according to the aging information, wherein the first voltage and the second voltage are reverse biased voltages.

Abstract: A memory device includes pages including memory cells arranged on a substrate. Voltages applied to first and second gate conductor layers and first and second impurity regions in each memory cell are controlled to retain a group of positive holes. The first and second impurity regions and first and second gate conductor layers are connected to source, bit, plate, and word lines. In a page write operation, a channel semiconductor layer is at a first data retention voltage. In a page erase operation, the group of positive holes are discharged by controlling the voltages, the channel semiconductor layer is at a second data retention voltage, a positive voltage pulse is applied to at least one of the word and plate lines of a selected page, and a ground voltage is applied to the word and plate lines of a non-selected page and to all of the source and bit lines.

Abstract: A non-volatile semiconductor memory device, described herein, comprises a bit line, a source line, a memory string comprising a plurality of memory cells connected in series between the source line and the bit line, and control circuitry coupled to the plurality of memory cells, the source line, and the bit line. The control circuitry is configured to: determine if a program operation is a single-bit program operation or multi-bit program operation; in response to the determination, identify a voltage level to set the source line to during performance of the program operation; and perform the program operation on the memory string, the program operation including setting the source line to the voltage level.

Abstract: Methods, systems, and devices for memory with parallel main and test interfaces are described. A memory die may be configured with parallel interfaces that may individually (e.g., separately) support evaluation operations (e.g., before or as part of assembly in a multiple-die stack) or access operations (e.g., after assembly in a multiple die stack). For example, a memory die may include a first set of one or more contacts that support communicating signaling with or via another memory die in a multiple-die stack. The memory die may also include a second set of one or more contacts that support probing for pre-assembly evaluations, which may be electrically isolated from the first set of contacts. By implementing such parallel interfaces, evaluation operations may be performed using the second set of contacts without damaging the first set of contacts, which may improve capabilities for supporting a multiple-die stack in a memory device.

Abstract: In a sense amplifier circuit, a first transistor is electrically connected between a first bitline and a first node, a first inverter includes a first input terminal and a first output terminal connected to the first node, and a second inverter includes a second input terminal connected to a second node and a second output terminal. A second transistor is electrically connected between the first output terminal and the second node, and a third transistor is electrically connected between the second output terminal and the first node. A precharge circuit transfers a first voltage to the first and second nodes during a first period, and transfers a second voltage higher than the first voltage to the first and second nodes during a second period.

Abstract: The disclosed computer-implemented method relating to read-only memory can include (i) asserting a column select signal to select a particular column within a column mux read-only memory, (ii) forwarding, in response to asserting the column select signal, a bit value stored at that particular column to a gate of a transistor that connects a first stage local bitline to a second stage local bitline, and (iii) forwarding an inversion of the bit value to the second stage local bitline through the drain of the transistor for local bitline sensing. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Methods for setting a resistance include applying a voltage across a memristive device, that exceeds a threshold based on a difference in chemical potential between a first material and a second material, to change a resistance of the memristive device. The memristive device includes a barrier layer of the second material that is formed between two metastable layers of the first material.

Abstract: An operating method of a non-volatile memory device that includes a plurality of cell strings each including a first stack and a second stack adjacent to the first stack, the operating method include performing a first program operation during a time period in which a plurality of program loops are performed, by applying a program voltage including a first plurality of voltage levels to a select word line connected to the first stack of each of the plurality of cell strings, applying, during the time period, second voltages including a second plurality of voltage levels to a non-select word line connected to the first stack of each of the plurality of cell strings, and maintaining, during the time period, a third voltage at a first level, the third voltage applied to a non-select word line connected to the second stack of each of the plurality of cell strings.

Abstract: A semiconductor storage according to an embodiment of the present disclosure includes two power source paths, and a connection path that connects the power source paths. Each of the power source paths includes a power gate transistor and a current source transistor which are coupled in series. The connection path connects ends of the respective power source paths on a side of the current source transistor. The semiconductor storage further includes a storage element, and a switch element inserted between the connection path and the storage element. A back gate is coupled to an internal node in the current source transistor provided in a low-side path of the two power source paths.

Abstract: A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.