Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines and disposed in strings and configured to retain a threshold voltage. The memory apparatus also includes a charge pump configured to ramp up to a program voltage in a pump setting process and supply the program voltage to the word lines during a program operation and ramp down from the program voltage in a pump resetting process. A control means is configured to successively apply one of a series of pulses of the program voltage from the charge pump to each selected one of the word lines to program the memory cells during the program operation. The control means is also configured to skip the pump setting process and the pump resetting process of the charge pump in between each of the series of pulses of the program voltage.

Abstract: A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.

Abstract: In some examples, a subword driver block of a memory device includes a first active region and a second active region adjacent to each other. The first active region forms drains/sources of a first and second transistors in a first region; the second active region forms drains/sources of a third and fourth transistors in a second region, where the first and second regions are adjacent to each other. The first, second, third and fourth transistors are coupled to a common non-active potential via a shared contact overlaid over a merged region between the first and second regions. The first and second active regions may comprise N+ diffusion materials.

Abstract: Methods, systems, and devices related to write broadcast operations associated with a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory device may enable write broadcast operations. A write broadcast may occur from one or more signal development components or from one or more multiplexers to multiple locations of the memory array.

Abstract: A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells.

Abstract: A computer system based on wafer-on-wafer architecture is provided, comprising a memory device and a logic circuit layer stacked in a wafer on wafer structural configuration. The memory device comprises a memory array and a circuit driver. The memory array comprises a shared circuit path and a plurality of memory cells, wherein the shared circuit path is connected to the memory cells. The circuit driver is connected to the shared circuit path, driving the memory cells. The logic circuit layer comprises a plurality of bonding pads for signal transmission, and a latency controller, connected to the memory array through the bonding pads, adjusting the number of memory cells connecting the shared circuit path, thereby dynamically adjusting the latency characteristics of the memory array. Embodiments of the memory device and the memory control method are also provided.

Abstract: A semiconductor storage device of an embodiment includes: a plurality of memory strings each including a plurality of memory cell transistors, the plurality of memory strings being connected in parallel to one another; and a control circuit configured to control a write operation on at least part of the plurality of memory cell transistors. The write operation is executed in response to reception of the write command and the address. The control circuit determines, based on the address, whether to perform a first voltage application operation before the write operation ends. The first voltage application operation applies a predetermined voltage to the plurality of word lines.

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes during a refresh operation, determining a respective row of a memory cells slated for refresh in each of a plurality of sections of a memory bank of a memory device, and determining whether the respective row of memory cells slated for refresh for a particular section of the plurality of sections of the memory bank has been repaired. The example method further includes in response to a determination that the row of memory cells slated for refresh has been repaired, cause a refresh within the particular section of the memory bank to be skipped while contemporaneously performing a refresh of the rows of memory cells slated for refresh in other sections of the plurality of sections of the memory bank to be refreshed.

Abstract: Embodiments provide an input buffer circuit and a semiconductor memory, a compensation subcircuit is provided between an input terminal of the input buffer circuit and a first terminal of a load subcircuit, a current of an output terminal of the input buffer circuit is increased, and voltage variation of the input terminal can be transmitted to the output terminal in time, such that the output terminal can timely receive the voltage variation of the input terminal, thereby avoiding distortion of an output signal, solving a problem of signal attenuation for the input buffer circuit, improving sensitivity of the input buffer circuit, and preventing negative effects from being caused to transmission of commands inside a system.

Abstract: An integrated circuit (IC) device configured for multiple return material authorizations (RMAs) is provided. The IC device includes an asset and a return material authorization (RMA) counter fuse including a first fuse, a second fuse, and a third fuse. The IC device enters an RMA state in response to blowing the first fuse, a second state in response to blowing the second fuse, and the RMA state in response to blowing the third fuse.

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.

Abstract: An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.

Abstract: Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include a gate material operable to modulate a conductivity between the first portions and the second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes a write transistor and a read transistor disposed over a substrate. The write transistor includes a write word line disposed on a plane that is substantially parallel to a surface of the substrate over the substrate, a write gate dielectric layer disposed over the write word line, a write channel layer disposed over the write gate dielectric layer, and a write bit line disposed over the substrate and extending in a direction substantially perpendicular to a surface of the substrate, and electrically connected to one end of the write channel layer. The read transistor includes a read channel layer disposed on the plane over the substrate, a read gate dielectric layer disposed over the read channel layer, and a read gate electrode layer disposed over the read gate dielectric layer and electrically connected to the other end of the write channel layer.

Abstract: A magnetoresistive memory cell includes a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer. The first magnetic tunnel junction and the second magnetic tunnel junction each are disposed on the metal layer; the metal layer is configured to pass write current, a projection line of an easy axis of the first magnetic tunnel junction on a plane where the metal layer is located forms a first angle against a direction of the write current, and a projection line of an easy axis of the second magnetic tunnel junction on the plane where the metal layer is located forms a second angle against a direction opposite to the direction of the write current; the first angle and the second angle are all less than 90°; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass read current.

Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting a state of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.

Abstract: Implementations described herein relate to a mixed write cursor for block stripe writing. In some implementations, a memory system may include one or more components that are configured to construct a block stripe associated with a write cursor, where the block stripe is associated with memory blocks from respective memory dies of a set of memory dies. The one or more components may be configured to program the first data to a first one or more memory blocks of the block stripe following a first logical write direction associated a logical order of the set of memory dies. The one or more components may be configured to program the second data to a second one or more memory blocks of the block stripe following a second logical write direction associated with the logical order of the set of memory dies.

Abstract: A storage system receives a request to read data that is located in a wordline undergoing a program operation. Instead of waiting for the program operation to complete, which would increase read latency, the storage system aborts the program operation and reconstructs the data from successfully-programmed memory cells in the wordline and from data latches associated with unsuccessfully-programmed memory cells in the wordline. The reconstructed data is then sent to the host. The program abort command can be similar to one used to provide a graceful shutdown in a power-loss situation.