Abstract: A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to receive a programming command with respect to a set of memory cells coupled to one or more wordlines of the memory device. The processing device is further to determine a value of a metric reflecting a state of the set of memory cells. The processing device is further to determine a delay based on the value of the metric. The processing device is further to perform a programming operation with respect to the subset of memory cells. The programming operation includes the delay between a first pass of the programming operation and a second pass of the programming operation.

Abstract: Implementations described herein relate to a mixed write cursor for block stripe writing. In some implementations, a memory system may include one or more components that are configured to construct a block stripe associated with a write cursor, where the block stripe is associated with memory blocks from respective memory dies of a set of memory dies. The one or more components may be configured to program the first data to a first one or more memory blocks of the block stripe following a first logical write direction associated a logical order of the set of memory dies. The one or more components may be configured to program the second data to a second one or more memory blocks of the block stripe following a second logical write direction associated with the logical order of the set of memory dies.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.

Abstract: A storage system receives a request to read data that is located in a wordline undergoing a program operation. Instead of waiting for the program operation to complete, which would increase read latency, the storage system aborts the program operation and reconstructs the data from successfully-programmed memory cells in the wordline and from data latches associated with unsuccessfully-programmed memory cells in the wordline. The reconstructed data is then sent to the host. The program abort command can be similar to one used to provide a graceful shutdown in a power-loss situation.

Abstract: A three dimension memory device, such as an AND-type memory, includes a memory cell tile, multiple source line switches, multiple first bit line switches to fourth bit line switches. The memory cell tile is divided into a first and a second memory cell sub-tiles. The first bit line switches are respectively coupled to multiple first bit lines of a first part of the first memory cell sub-tile. The second bit line switches are respectively coupled to multiple second bit lines of a second part of the first memory cell sub-tile. The third bit line switches are respectively coupled to multiple third bit lines of a first part of the second memory cell sub-tile. The fourth bit line switches are respectively coupled to multiple fourth bit lines of a second part of the second memory cell sub-tile.

Abstract: An integrated circuit memory includes a first memory block and an adjacent second memory block. The first memory block comprises a first memory pillar around which a first memory cell is formed. The second memory block comprises a second memory pillar around which a second memory cell is formed. An isolation or slit area between the first and second memory blocks electrically isolates the first and second memory blocks. In an example, the slit area comprising a slit pillar around which no memory cells are formed. The slit pillar is a dummy pillar, and insulator material electrically isolates the slit pillar from a Word Line (WL) through which it passes. The isolation layer electrically can also isolate a (WL) of the first memory block from a corresponding WL of the second memory block. In an example, the slit pillar and the memory pillars have at least in part similar structures.

Abstract: Semiconductor devices are provided. A write port circuit is configured to perform a write function according to the write word line and the first and second write bit lines. The first read port circuit is configured to perform first read function according to the first read bit line and the first read word line. The second read port circuit is configured to perform second read function according to the second read bit line and the second read word line. The transistors of the first and second read port circuits share a first active structure extending in the first direction. The first read bit line and the second read bit line extend in the first direction in a first metallization layer, and the first write bit line and the second write bit line extend in the first direction in a second metallization layer over the first metallization layer.

Abstract: A multi-channel memory device includes N first memory blocks, a first redundancy memory block, and N first interface circuits. Each of the first interface circuits is coupled to two of the first memory blocks and the first redundancy memory block. The first interface circuits respectively select N first selected memory blocks in the first memory block and the first redundancy memory block according to a plurality of first selection signals, where N is a positive integer greater than 1.

Abstract: Examples described herein relate to a device that includes: a first power rail to provide a signal from a power source to a reference supply voltage pin of a memory controller; a second power rail to provide a signal from the power source to an output buffer pin of the memory controller and to an output buffer pin of a central processing unit (CPU). In some examples, the second power rail is separate from the first power rail, during a high power state, the power source is to supply a same voltage to each of the reference supply voltage pin, the output buffer pin of the memory controller, and the output buffer pin of the CPU, and during a connected standby state, the power source is to reduce voltage provided to the output buffer pin of the memory controller and the output buffer pin of the CPU using the second power rail and maintain a voltage provided to the reference supply voltage pin.

Abstract: A readout circuit architecture and a sense amplification circuit are provided. The readout circuit architecture includes: a readout amplification unit including a first P-type transistor and a second P-type transistor; and a first offset compensation unit including a first offset compensation transistor and a second offset compensation transistor. The first P-type transistor is arranged in a first area and the second P-type transistor is arranged in a second area. When the first area and the second area are arranged at interval in a first direction, the first offset compensation transistor and the second offset compensation transistor are arranged in a third area located between the first area and the second area. When the first area and the second area are arranged adjacently in the first direction, the first offset compensation transistor is arranged in a fourth area and the second offset compensation transistor is arranged in a fifth area.

Abstract: A nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of word-lines, a plurality of memory cells provided in a plurality of channel holes and a word-line cut region extending in a first horizontal direction and dividing the word-lines into a plurality of memory blocks. A plurality of target memory cells coupled to each of the plurality of word-lines are grouped into outer cells and inner cells based on a location index of each of the plurality of memory cells. The control circuit controls a program operation on target memory cells coupled to a target word-line of the plurality of word-lines such that each of the outer cells stores a first number of bits and each of the inner cells stores a second number of bits. The second number is a natural number greater than the first number.

Abstract: A memory device coupled to a memory controller and including a memory array and an access circuit is provided. The memory array includes a plurality of cells. Each of the cells is coupled to a word-line. The access circuit is coupled between the memory controller and the memory array. In a normal mode, the access circuit executes a refresh action for the cells which are coupled to at least one word-line in response to the memory controller outputting an auto-refresh command. In a standby mode, the access circuit selects one of the word-lines and determines whether to execute the refresh action for the cells coupled to the selected word-line according to the retention capability of the selected word-line at regular time intervals.

Abstract: A memory device includes a memory cell that stores data. The memory device also includes a pair of digit lines that carry the data from the memory cell. The memory device further includes a sense amplifier that senses and amplifies voltages received at the pair of digit lines. The memory device also includes a replica sense amplifier that generates a replica common mode voltage associated with a common mode voltage of the pair of digit lines.

Abstract: A storage device includes: a controller that exchanges data with a host through an interface; memory devices that store the data; a power supply circuit that outputs internal voltages, required for the controller and the memory devices, using an external voltage received through the interface; a distribution circuit that provides an operating voltage to the memory devices; and a discharge circuit including a first comparator that compares a first internal voltage, among the internal voltages, with a reference voltage and a second comparator that compares a second internal voltage, different from the first internal voltage, with the reference voltage, and including an operating circuit that computes an output of the first comparator and an output of the second comparator to output a discharge control signal determining whether the operating voltage has been discharged.

Abstract: The present technology relates to an electronic device. According to an embodiment of the present disclosure, a memory device may include a plurality of memory cells connected to each word line, a peripheral circuit configured to perform a program operation on memory cells that are connected to a selected word line, and a control logic configured to control the peripheral circuit to perform the program operation on the memory cells that are connected to the selected word line after performing a pre-program operation that increases a threshold voltage of over-erasure cells, among memory cells that are connected to an adjacent word line, having a threshold voltage of an over-erasure state that is lower than a threshold voltage of an erasure state, to the threshold voltage of the erasure state, wherein the adjacent word line is a word line that is next to the selected word line.

Abstract: A local amplifying circuit, a data readout method and a memory are provided. The local amplifying circuit includes: write control transistors, configured to connect a global data line to a local data line based on a write enable signal; column selection transistors, configured to connect a bit line to the local data line based on a column selection signal; a first control NMOS transistor, having a gate connected to the local data line, one of a source and a drain being connected to the global data line and the other being connected to a corresponding read control transistor; a second control NMOS transistor, having a gate connected to a complementary local data line, one of a source and a drain being connected to a complementary global data line and the other being connected to a corresponding read control transistor.

Abstract: Methods, systems, and devices for sense amplifier with digit line multiplexing are described. A method includes precharging an input and an output of an amplifier stage of a sense component to a first voltage based on a read operation associated with a memory cell. The method includes precharging a first side and a second side of a latch stage of the sense component to the first voltage based on precharging the output of the amplifier stage to the first voltage, the latch stage coupled with the amplifier stage. The method may also include coupling a second voltage from a digit line associated with the memory cell to the input of the amplifier stage, the amplifier stage generating a third voltage on the output based on coupling the second voltage to the input, and the latch stage latching a logic value associated with the memory cell based on the third voltage.

Abstract: Exemplary methods, apparatuses, and systems include allotting an initial amount of volatile memory to a write buffer. The write buffer stores batches of data to be written to non-volatile memory. In response to detecting a trigger to update the write buffer configuration, the volatile memory allotted to the write buffer is reduced.

Abstract: An example method of two-stage voltage calibration upon power-up of a memory device comprises: identifying a set of memory pages that have been programmed within a time window; responsive to detecting a power up event, performing a first calibration operation with respect to the set of memory pages to determine a first value of a data state metric; identifying, among a plurality of voltage offset bins, a first voltage offset bin corresponding to the first value of the data state metric; storing, in a temporary metadata table, a first record associating the set of memory pages with the first voltage offset bin; performing a second calibration operation with respect to the set of memory pages to determine a second value of the data state metric, wherein a second accuracy of the second calibration operation exceeds a first accuracy of the first calibration operation; identifying, among a plurality of voltage offset bins, a second voltage offset bin corresponding to the second value of the data state metric; and

Abstract: A quadrature error correction circuit includes a duty cycle adjusting circuit, a phase interpolator, a phase detector, and a delay control circuit. The duty cycle adjusting circuit generates a first corrected clock signal and a second corrected clock signal whose skew and duty cycle error are concurrently adjusted by adjusting a delay of edges of a second clock signal and adjusting a delay of a falling edge of a first clock signal based on first through fourth control code sets. The phase interpolator generates a second delayed and selected clock signal by delaying a second selected clock signal selected from first through fourth adjusted clock signals. A phase detector detects a phase difference between a first selected clock signal and the second delayed and selected clock signal to generate an up/down signal. The delay control circuit generates the first through fourth control code sets based on the up/down signal.