Abstract: A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. The on-die ECC engine, in the test mode, cuts off a connection with the memory cell array, receives a test data, stores the test data in the first latch, performs an ECC decoding on the test data stored in the first latch and a test parity data, stored in the second latch in response to a read command and provides an external device with a severity signal indicating whether the test data and the test parity data includes at least one error bit and the at least one error bit is correctable.

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

Abstract: A method and apparatus with flash memory control are provided. The method includes performing first programming on a target memory cell of a cell array while adjusting a first programming time and a programming voltage, when a cell current of the target memory cell is determined to satisfy a primary target in association with the first programming, performing second programming on the target memory cell while adjusting a second programming time, and when the cell current of the target memory cell is determined to satisfy a secondary target in association with the second programming, terminating programming on the target memory cell.

Abstract: Memory devices are disclosed. A device may include a number of word line drivers, wherein each word line driver of the number of word line drivers including a first transistor and a second transistor. The device may also include a number of first driver gates, wherein the first transistor of each word line driver has a gate coupled to a dedicated first driver gate of the number of driver gates. Further, the device may include a second driver gate coupled to a gate of each second transistor of each of the number of word line drivers. Associated circuits, methods, and systems are also disclosed.

Abstract: A semiconductor storage device according to an embodiment comprises: a first memory circuit; a second memory circuit having a storage capacity smaller than that of the first memory circuit; a readout line commonly connected to the first memory circuit and the second memory circuit; a sense amplifier configured to compare a voltage of a first bit signal or a second bit signal with a reference voltage, where the first bit signal being inputted from the first memory circuit through the readout line and the second bit signal being inputted from the second memory circuit through the readout line; and a readout conditioning circuit configured to change at least one of an operation timing of the sense amplifier and the reference voltage corresponding to the first bit signal and the second bit signal.

Abstract: A method for manufacturing an OxRAM type resistive memory cell including a silicon oxide layer, the method including determining manufacturing parameter values enabling the resistive memory cell to have an initial resistance between 107? and 3·109?; and forming on a substrate a stack successively including a first electrode, the silicon oxide layer and a second electrode, by applying the manufacturing parameter values.

Abstract: A two-dimensional material-based selector includes: a stack unit, wherein the stack unit has a metal-two-dimensional semiconductor-metal structure comprising a two-dimensional semiconductor layer, and metal layers arranged on an upper surface and a lower surface of the two-dimensional semiconductor layer, respectively. The number of the stack units is N, where N?1. In each stack unit, a Schottky contact is formed on two metal-two-dimensional conductor interfaces, and the stack unit includes two Schottky diode structures connected in reverse series in response to the two-dimensional material-based selector being turned on. Alternatively, the number of the stack units is M, where M?2. In each stack unit, a Schottky contact and an Ohmic contact are formed the two metal-two-dimensional conductor interfaces, respectively. The M stack units include M Schottky diode structures connected in reverse series in response to the two-dimensional material-based selector being turned on.

Abstract: The disclosed technology relates to a magnetic domain wall-based memory device including a combination of at least one magnetic domain wall track and at least one spin orbit torque (SOT) track, which are arranged in a crossing architecture. The SOT track can include a first strip of a patterned SOT generating layer, wherein the first strip extends into a first direction and is configured to pass a first current along the first direction. The magnetic domain wall track can include a second strip of the patterned SOT generating layer and a first magnetic strip of a patterned magnetic free layer, wherein the second strip extends along a second direction and intersects with the first strip in a first crossing region. The first magnetic strip can be provided on the second strip including the first crossing region and can be configured to pass a second current along the second direction.

Abstract: A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.

Abstract: A semiconductor memory device includes a memory cell array, a row decoder and a timing/voltage control circuit. The memory cell array is divided into a plurality of row blocks by one or more row block identity bits, and each of the of row blocks includes sub-array blocks arranged in a first direction. A row address includes the one or more row block identity bits. The row decoder activates a first word-line coupled to a first memory cell, activates a second word-line coupled to a second memory cell in response to the row address, and outputs a row block information signal. The timing/voltage control circuit adjusts at least one of an operation interval and an operation voltage of a memory operation on the first memory cell and the second memory cell according to a distance in a second direction crossing the first direction from a reference position, based on the row block information signal.

Abstract: A data transmission system includes a first integrated circuit. The first integrated circuit includes a first mixing terminal coupled to a first power supply voltage terminal at a point internal to the first integrated circuit, a first return terminal, a first resistor having a first terminal coupled to the first mixing terminal, and a second terminal for providing a first mixed voltage, and a second resistor having a first terminal coupled to the second terminal of the first resistor, and a second terminal coupled to the first return terminal.

Abstract: A memory system may include: a non-volatile memory device, a volatile memory device suitable for defining, as cold data, data stored in a word line, on which a refresh operation is performed a number of times greater than a reference number among a plurality of word lines coupled to a volatile memory cell array, and evicting the cold data, and a controller suitable for controlling operations of the volatile memory device and the non-volatile memory device, and storing the evicted cold data into the non-volatile memory device.

Abstract: A memory circuit comprises a signal buffer, a plurality of switch circuits, a temperature sensor, a path-length-compensation circuit and at least one data latch. The signal buffer is configured to receive a strobe signal. The plurality of switch circuits are coupled to the signal buffer through a plurality of signal paths respectively, wherein the lengths of the plurality of signal paths are equal. The temperature sensor is coupled to the plurality of switch circuits and configured to conduct one of the plurality of switch circuits according to temperature of the memory circuit. The path-length-compensation circuit comprises a plurality of input terminals connected in series, which are configured to respectively receive outputs of the plurality of switch circuits. The at least one data latch is coupled to an output terminal of the path-length-compensation circuit and configured to store or output data according to output of the path-length-compensation circuit.

Abstract: The present technology includes: a current mirror configured to apply a test current that is generated by a test voltage to a selected word line, among a plurality of word lines, and to generate a copy current by copying the test current; a comparison circuit configured to compare at least one reference current with the copy current to generate a comparison result signal; and a test control circuit configured to perform a first noise control mode that charges unselected word lines, among the plurality of word lines, with electric charges, in response to a test mode signal and floats the unselected word lines.

Abstract: A first insulating layer 21 is disposed on a substrate 20. N+ layers 2 are separated from the insulating layer and in directions horizontal and vertical to the substrate. P layers 1 contact the n+ layers 2 and extend in the horizontal direction. N+ layers 3 contact the p layers 1. Gate insulating layers 4 cover the p layers 1 and part of the n+ layers 2 and 3. Second gate conductor layers 6 are electrically separated from a first gate conductor layer 5 contacting the gate insulating layers 4. A conductor layer 12 contacts the n+ layers 2. A conductor layer 13 contacts the n+ layers 3. A second insulating layer 22 contacts the first gate conductor layer 5, the n+ layers 2, and the conductor layer 12. A third insulating layer 23 contacts the second gate conductor layers 6, the n+ layers 3, and the conductor layer 13.

Abstract: A sense amplifier capable of performing a logical NOT operation is provided, which includes a sense circuit, configured to sense a first voltage of a bit line and a second voltage of an inverse bit line; a first transistor, coupled between a first terminal of the sense circuit and the bit line; a second transistor, coupled between a second terminal of the sense circuit and the inverse bit line; and a third transistor, coupled between the bit line and the inverse bit line. First and second memory cells are respectively controlled by first and second word lines, and connected to the bit line. When the sense amplifier is in an inverse writing state, the sense amplifier writes the second voltage to the second memory cell through a predetermined path. A first logical state of the first voltage is complementary to a second logical state of the second voltage.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first gate structure, a second gate structure, and a first active region. The first gate structure extends along a first direction and is electrically connected to a first transistor. The second gate structure extends along the first direction and is electrically connected to a second transistor. The first active region extends along a second direction different from the first direction and across the first gate structure and the second gate structure. The first gate structure and the first active region collaboratively form a first fuse element. The second gate structure and the first active region collaboratively form a second fuse element.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory controller may include a training controller, a training data storage, and a machine learning processor. The training controller may perform training of correcting interface signals exchanged with a memory device, generate training data that is a result of the training, and output the training data as sample training data based on a comparison result of a training reference and the training data. The training data storage may store training history information including plural pieces of sample training data. The machine learning processor may update the training reference through machine learning based on the training history information.

Abstract: A memory array is disclosed. The memory array includes a plurality of memory cells disposed over a substrate. Each of the memory cells is coupled to a corresponding one of a plurality of word lines and a corresponding one of a plurality of bit line pairs. First four of the memory cells that are coupled to four consecutive ones of the word lines and to a first one of the bit line pairs are abutted to one another on the substrate along a single lateral direction.

Abstract: A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit coupled between the current control circuit and a ground. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. First terminals of the first transistors each is in connection with one of the bit lines. Second terminals of the first transistors each is in connection with the discharge enable circuit. Third terminals of the first transistors are in connection with a reference current generator of the current control circuit.