Patents Examined by Mushfique Siddique
  • Patent number: 10468095
    Abstract: A method of operating a memory device includes providing a first voltage to a memory array, providing a second voltage to a peripheral logic circuit, receiving an access request, and in response to the access request, increasing a third voltage of a bit line of the memory array during a precharge phase.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: November 5, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Piyush Jain, Vivek Asthana, Naveen Batra
  • Patent number: 10468104
    Abstract: The present disclosure relates to a structure which includes a pair of non-volatile storage devices in a memory array which are sensed to determine an initial data state and reinforced by a write operation of the initial data state to the pair of non-volatile storage devices. The structure can be used for a robust and error free physical unclonable function.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Darren L. Anand, William Roy John Corbin
  • Patent number: 10460792
    Abstract: To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: October 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Motoo Suwa, Takafumi Betsui
  • Patent number: 10460814
    Abstract: Embodiments of the present disclosure generally relate to non-volatile memory devices, such as flash memory, and sensing operation methods including locking out high conduction current memory cells of the memory devices. In one embodiment, a method of sensing a plurality of memory cells in an array includes conducting a lower page read of one or more demarcation threshold voltages. Each memory cell is programmable to a threshold voltage corresponding to one of multiple memory states. A middle page read of one or more demarcation threshold voltages is conducted. Memory cells identified from the lower page read are selectively locked out during the middle page read. An upper page read of one or more demarcation threshold voltages is conducted. Memory cells identified from a prior page read are selectively locked out during the upper page read.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 29, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Piyush Dak, Mohan Vamsi Dunga, Pitamber Shukla
  • Patent number: 10453524
    Abstract: A semiconductor memory device, a flash memory and a continuous reading method thereof are provided for achieving a continuous reading of pages in high speed. A flash memory of the invention includes a memory cell array; a page reading element, which selects a page of the memory cell array and reads out data of the selected page to a page buffer/sense circuit; a page information storage element, which stores page information related to a range of a continuous reading; and a control element, which controls the continuous reading of the page. The control element determines whether to resume the continuous reading according to the page information. When it is determined to resume the continuous reading, the continuous reading can still be performed without a page data read command and a page address being inputted even if a chip select signal is toggled.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 22, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Takehiro Kaminaga, Katsutoshi Suito
  • Patent number: 10453521
    Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Yeop Baeck, Tae-Hyung Kim, Daeyoung Moon, Dong-Wook Seo, Inhak Lee, Hyunsu Choi, Taejoong Song, Jae-Seung Choi, Jung-Myung Kang, Hoon Kim, Jisu Yu, Sun-Yung Jang
  • Patent number: 10446243
    Abstract: A control method for a storage device is provided. The storage device includes a memory controller and a flash memory. The flash memory includes multiple blocks. The control method includes the following steps. Maintain a state table by the memory controller, wherein the state table records a disturbance count and a last check time of the blocks in the flash memory. Trigger a probe operation on a target block in the flash memory when at least one of the following conditions is met: (a) the disturbance count of the target block is greater than or equal to a disturbance count threshold; and (b) an elapsed time period of the target block is greater than or equal to an elapsed time threshold, wherein the elapsed time period of the target block starts from the last check time of the target block.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 15, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Tzu-Yi Yang, Yung-Sheng Chen
  • Patent number: 10438658
    Abstract: Provided is a non-volatile memory device comprising a plurality of memory cells and memory control logic that when executed performs operations comprising initiating a refresh operation; in response to the refresh operation, performing a read of the memory cells to read values of the memory cells; determining whether the read memory cells have a first value or a second value; and for the memory cells determined to have the first value, rewriting the determined first value to the memory cell, wherein the rewriting operation is not performed with respect to memory cells determined to have the second value.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: October 8, 2019
    Assignee: INTEL CORPORATION
    Inventors: Ningde Xie, Robert W. Faber
  • Patent number: 10438681
    Abstract: A semiconductor integrated circuit device may include a plurality of semiconductor chips, a scribe lane, connecting wiring, and a selection circuit. Each of the semiconductor chips may include a peripheral circuit. The scribe lane may be positioned between the semiconductor chips. A test pad may be arranged in the scribe lane. The connecting wiring may be connected between the test pad and the peripheral circuit. The selection circuit may be configured to selectively connect or disconnect the connecting wiring.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 8, 2019
    Assignee: SK hynix Inc.
    Inventor: Kwi Dong Kim
  • Patent number: 10431305
    Abstract: A high-performance on-module caching architecture for hybrid memory modules is provided. A hybrid memory module includes a cache controller, a first volatile memory coupled to the cache controller, a first multiplexing data buffer coupled to the first volatile memory and the cache controller, and a first non-volatile memory coupled to the first multiplexing data buffer and the cache controller, wherein the first multiplexing data buffer multiplexes data between the first volatile memory and the first non-volatile memory and wherein the cache controller enables a tag checking operation to occur in parallel with a data movement operation. The hybrid memory module includes a volatile memory tag unit coupled to the cache controller, wherein the volatile memory tag unit includes a line connection that allows the cache controller to store a plurality of tags in the volatile memory tag unit and retrieve the plurality of tags from the volatile memory tag unit.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 1, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Amin Farmahini Farahani, David A. Roberts
  • Patent number: 10424366
    Abstract: A semiconductor memory device includes a memory cell array to which a plurality of word lines are coupled, a voltage generation circuit configured to apply operating voltages to the plurality of word lines during a program operation, and a control logic configured to control the voltage generation circuit to perform a discharge operation for the plurality of word lines when an external power supply voltage is reduced during the program operation, wherein the control logic controls the voltage generation circuit such that, during the discharge operation, a potential level of a selected word line among the plurality of word lines is discharged, and then potential levels of the other unselected word lines are discharged.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 24, 2019
    Assignee: SK hynix Inc.
    Inventor: Deung Kak Yoo
  • Patent number: 10418116
    Abstract: A semiconductor memory device includes a memory cell array and a control logic. The memory cell array includes a plurality of memory blocks. The control logic groups the memory blocks, determines driving voltages to be respectively applied to the groups, and applies each of the determined driving voltages to memory blocks included in a corresponding group to control the operation of the memory cell array.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: September 17, 2019
    Assignee: SK hynix Inc.
    Inventors: Min Sang Park, Myoung Kwan Cho
  • Patent number: 10418090
    Abstract: Systems and methods include capture circuitry configured to capture a write signal from a host device using a data strobe signal from the host device and to output one or more indications of capture of the write signal. Calculation circuitry is configured to receive the data strobe signal, receive the one or more indications of capture, and determine a delay between a first edge of the data strobe signal and receipt of the one or more indications of capture. The systems and methods also include transmission and control circuitry configured to launch subsequent write signals at a time based at least in part on the delay.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Ming-Bo Liu, Daniel B. Penney
  • Patent number: 10410717
    Abstract: A memory device according to an embodiment includes a first interconnect, a second interconnect, a first variable resistance member, a third interconnect, a second variable resistance member, a fourth interconnect, a fifth interconnect and a third variable resistance member. The first interconnect, the third interconnect and the fourth interconnect extend in a first direction. The second interconnect and the fifth interconnect extend in a second direction crossing the first direction. The first variable resistance member is connected between the first interconnect and the second interconnect. The second variable resistance member is connected between the second interconnect and the third interconnect. The third variable resistance member is connected between the fourth interconnect and the fifth interconnect. The fourth interconnect is insulated from the third interconnect.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kikuko Sugimae, Yusuke Arayashiki
  • Patent number: 10410720
    Abstract: A semiconductor memory device includes a first conductor extending in a first direction and a second conductor extending in a second direction and disposed above the first conductor in a third direction. Third and fourth conductors extend in the first direction and adjacent to each other in the second direction. The third and fourth conductors are above the second conductor. A fifth conductor includes a variable resistance unit and is between the first and second conductors. A sixth conductor includes a variable resistance unit and is between the third and second conductors. A seventh conductor includes a variable resistance unit and is between the fourth and second conductors. A center point of the fifth conductor along a width of the fifth conductor is does not fully overlap with either of the sixth or seventh conductors along the third direction.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: September 10, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takahiko Iizuka, Daisaburo Takashima, Ryu Ogiwara
  • Patent number: 10403387
    Abstract: Disclosed is a memory device including a plurality of memory cell arrays each of which includes a normal cell array and a redundant cell array, a first fuse unit including a plurality of first fuse sets corresponding to first memory cell arrays among the memory cell arrays, a second fuse unit including a plurality of second fuse sets corresponding to second memory cell arrays among the memory cell arrays, the first fuse sets corresponding to the second fuse sets, respectively, and a repair unit selecting a pair of fuse sets that correspond to each other from the first fuse sets and the second fuse sets based on information that represents whether each of the first fuse sets and the second fuse sets failed or is usable and programming a repair target column address of the memory cell arrays in the selected fuse set pair.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Jung-Taek You
  • Patent number: 10403373
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 3, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
  • Patent number: 10403389
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 10402202
    Abstract: A pipe latch circuit includes: a pipe latch control block suitable for controlling a plurality of pipe input signals and a plurality of pipe output signals to be activated sequentially or be divided into at least two groups and be activated sequentially by group, depending on a latency setting value, and outputting at least one pipe input signal and at least one pipe output signal; and a pipe latch block coupled between an input node and an output node, and suitable for storing data of the input node in response to the pipe input signal and outputting stored data to the output node in response to the pipe output signal.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: September 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Yun-Gi Hong
  • Patent number: 10403366
    Abstract: In general, embodiments of the technology relate to a method for adjusting solid state memory write parameters. The method includes obtaining a performance goal for the solid state memory, receiving a client write request for data from a client, where the client write request comprises a logical address and data to be written. The method further includes determining a physical address corresponding to the logical address, where the physical address comprises a page number for a physical page in the persistent storage, obtaining at least one verify threshold value using the performance goal, issuing a control module program request including the data to be written and the at least one verify threshold value to a storage module, where the storage module comprises the physical page, and programming the data into the physical page of the storage module using the at least one verify threshold value.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: September 3, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Haleh Tabrizi, Seungjune Jeon, Andrew Cullen