Patents Examined by Mushfique Siddique
  • Patent number: 11328763
    Abstract: A semiconductor memory device includes a common driver suitable for generating a preliminary driving signal according to a voltage at a first node; and a plurality of individual drivers suitable for providing a core voltage to a sense amplifying circuit of a corresponding one of a plurality of cell mats, according to the preliminary driving signal, wherein each of the individual drivers includes: a level shifting circuit suitable for outputting a main driving signal by shifting a level of the preliminary driving signal when a corresponding mat select signal and a pull-up driving signal are activated; a pull-up driver suitable for driving a pull-up power line with the core voltage according to the main driving signal; and a switch suitable for coupling the first node to the pull-up power line when the corresponding mat select signal and the pull-up driving signal are activated.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventor: Jong Man Im
  • Patent number: 11315622
    Abstract: A multi-phase clock generator has a set of transistors, a first latch, and a second latch. The set of transistors may be arranged in a sense amplifier latch architecture, in which the set of transistors include a first inverter and a second inverter. The first inverter may provide a first phase data strobe signal and the second inverter may provide a second phase data strobe signal. The first latch and the second latch are coupled to the set of transistors. The set of transistors may receive a first portion of current at the first inverter and a second portion of current at the second inverter. The set of transistors may amplify the first portion of current in response to the first portion being greater than the second portion. The set of transistors may also drive the first phase data strobe signal using the amplified first portion.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Parthasarathy Gajapathy, Brian J. Ladner
  • Patent number: 11315637
    Abstract: Aspects of a storage device including a memory and controller are provided which allow for erase voltages applied during erase operations to be adaptively changed at elevated temperatures to reduce erase time and prevent erase failures. In response to detecting a lower temperature of the memory, the controller applies a first erase voltage to cells in a block of a die, and in response to detecting a higher temperature of the memory, the controller applies a second erase voltage larger than the first erase voltage to the cells in the block of the die. The controller may apply the different erase voltages depending on whether the temperature of the die falls within respective temperature ranges or meets a respective temperature threshold, which may change for different dies. As a result, successful erase operations at higher temperatures may be achieved.
    Type: Grant
    Filed: June 3, 2020
    Date of Patent: April 26, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kranthi Kumar Vaidyula, Amiya Banerjee, Phani Raghavendra Yasasvi Gangavarapu
  • Patent number: 11315627
    Abstract: Methods, systems, and devices for voltage drop mitigation techniques for memory devices are described. A memory device may include an array of memory cells, a conductive line, a pull-up circuit, and an output circuit. The conductive line may be configured to convey a first voltage for performing an operation with the array of memory cells. The pull-up circuit may be configured to couple the conductive line with a voltage source during at least a portion of a duration in which the operation is performed based on a first signal that enables applying a current to the array of memory cells as part of the operation. The output circuit may be configured to output a second signal to deactivate the pull-up circuit before the operation is complete. Outputting the second signal may be based on the first signal and a difference between the first voltage and a reference voltage.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: April 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Wei Lu Chu, Dong Pan
  • Patent number: 11309016
    Abstract: A variable-latency computing device includes a computing module, enabling units, a storage operation unit, and a detecting controller. The enabling units are divided into at least two groups. The storage operation unit includes word lines and bit lines. The enabling units enable the word line. The storage operation unit accumulates the data values corresponding to the bit lines and the enabled word line, thereby computing first accumulation values. The detecting controller controls the computing module to stop receiving the first accumulation values when the sum of the first accumulation values is higher than a threshold value and takes turns to turn off the at least two groups. The storage operation unit computes second accumulation values during different periods. The computing module receives and computes the second accumulation values corresponding to the at least two groups, so as to generate a computation value.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: April 19, 2022
    Assignee: NATIONAL CHUNG CHENG UNIVERSITY
    Inventors: Tay-Jyi Lin, Yu Chia Hu, Yi-Hsuan Ting, Jinn-Shyan Wang
  • Patent number: 11302378
    Abstract: The disclosure relates to an initialization circuit for initializing memory cells of a memory array. The individual memory cells are coupled to a common bit line of the memory array via at least one pass element of the individual memory cells. Each individual memory cell comprises a charge-based storage element including a capacitance. The initialization circuit activates the pass elements of a plurality of the memory cells to be initialized such that the capacitances of the plurality of memory cells are connected simultaneously to the common bit line. Further, aspects of the disclosure relate to a method for initializing memory cells and a semiconductor circuit.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: April 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Martin Bernhard Schmidt, Peter Altevogt, Wolfgang Gellerich, Juergen Pille, Christoph Raisch
  • Patent number: 11295807
    Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes volatile memory cells located along a pillar that has a length extending in a direction perpendicular to a substrate of a memory device. Each of the volatile memory cells includes a capacitor and at least one transistor. The capacitor includes a capacitor plate. The capacitor plate is either formed from a portion a semiconductor material of the pillar or formed from a conductive material separated from the pillar by a dielectric.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Yoshihito Koya
  • Patent number: 11295832
    Abstract: Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways depending, for example, on a relationship between cell plates of the group of cells, pages of cells, and/or sections of cells. Cells may be selected in pairs or in larger multiples in order to accommodate an electric current relationship (such as a short) between two or more cells within a group, a page, and/or a section. When performing an access based on a smaller page size, a larger page size of cells may be selected to accommodate a short between plates within the smaller page, the larger page, and/or a section of memory that includes the smaller page or the larger page.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Simon J. Lovett, Richard E. Fackenthal
  • Patent number: 11288009
    Abstract: The present disclosure is directed to read sample offset most probable bit operation associated with a memory component. A processing device performs a first read, a second read, and a third read of data from the memory component using a center value corresponding to a read threshold voltage value, a negative offset value, and a positive offset value, respectively. The processing device performs a most probable bit operation on the first set of data, the second set of data, and the third set of data to generate a most probable bit sequence corresponding to the data associated with the memory component. The processing device can store or output the generated most probable bit sequence.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: March 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Sheperek, Bruce A. Liikanen
  • Patent number: 11289167
    Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 29, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Takayuki Akamine, Masanobu Shirakawa, Tokumasa Hara
  • Patent number: 11289152
    Abstract: An in-memory computing device including a plurality of memory cell arrays and a plurality of sensing amplifiers are provided. The memory cell arrays respectively receive a plurality of input signals. The input signals are divided into a plurality of groups. The groups respectively have at least one partial input signal. The at least one partial input signal of each of the groups has a same value. Numbers of the at least one partial input signal in the groups sequentially form a geometric sequence with a common ration equal to 2. The memory cell arrays respectively provide a plurality of weightings, and perform multiply-add operations respectively according to the received input signals and the weightings to generate a plurality of computation results. The sensing amplifiers respectively generate a plurality of sensing results according to the computation results.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: March 29, 2022
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Ming-Liang Wei, Po-Kai Hsu, Hang-Ting Lue, Teng-Hao Yeh
  • Patent number: 11276467
    Abstract: A vertical NAND string in a channel-stacked 3D memory device may be programmed using ISPP scheme, wherein a preparation step is introduced immediately after each verification step and before the start of a corresponding verification step. During the preparation step, the electrons accumulated in the channel may be drained by the selected bit line for enhancing the coupling effect of the channel, thereby reducing program disturb and increasing program speed.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 15, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Hongtao Liu, Lei Jin, Shan Li, Yali Song
  • Patent number: 11257537
    Abstract: Provided are a voltage generator circuitry for generating an internal power supply voltage of a memory device and an operation method thereof. In the memory device, a voltage generator circuitry generates a first internal power supply voltage when the memory device is in an active mode, generates a second internal power supply voltage when the memory device is in a standby mode, and provides the first internal power supply voltage or the second internal power supply voltage to an internal power supply voltage line for using as an internal power supply voltage of the memory device. When the memory device is in the standby mode, the voltage generator circuitry blocks generation of the first internal power supply voltage by using a first voltage higher than an external power supply voltage.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: February 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Sanghoon Jung
  • Patent number: 11250904
    Abstract: Voltages loaded onto the bit lines in a first CA section of a memory array can be latched by enabling the BLSA between the first section and a second section adjacent to the first section causing latched voltages to propagate to bit lines in the second section. Voltages propagated to the bit lines in the second section using the latches between the second section and a third section. Voltages can be propagated sequentially from section to subsequent adjacent section until a target location is reached. The scheme can be applied as a method of page-data write access in a memory chip, of which page data can be propagated sequentially from section to subsequent adjacent section until a target location is reached, and then, activating a word line in a section of the memory comprising the target location to write voltages to the memory cells at the target location.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: February 15, 2022
    Assignee: Piecemakers Technology, Inc.
    Inventors: Gyh-Bin Wang, Tah-Kang Joseph Ting, Ming-Hung Wang
  • Patent number: 11244716
    Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a wordline driving circuit including a plurality of sub-wordline decoders respectively connected to the plurality of wordlines, wherein each of the sub-wordline decoders is configured to input a first driving signal to the respectively connected wordline when the wordline is selected, and wherein each sub-wordline decoder is configured to input a predetermined power supply voltage to the respectively connected wordline when the wordline is unselected, The memory device may include a sense amplifier circuit including sense amplifiers connected to the bitlines, and a logic circuit configured to determine a failure of at least one of the memory cell array and the wordline driving circuit.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: February 8, 2022
    Inventors: Jinseok Jeong, Eunju Gi
  • Patent number: 11238909
    Abstract: Apparatuses and methods for setting operational parameters of a memory based on location are disclosed. The operational parameters may include operational parameters for an input/output circuit. For example, operational parameters may be for output driver circuit impedance, equalization for input receiver circuits, termination impedance, as well as others. Location information is provided to a memory device and used for setting the operational parameter. A nominal operational parameter setting may be offset based on the location information, thereby tailoring the operational parameter of the memory device according to location in some examples. The location information may be memory slot address for location based on memory module location. The location information may be related to a location of a memory device within a sub-system. The location information may be provided to unused terminals of a memory device, for example, unused data terminals in some examples.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: February 1, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Elancheren Durai, Quincy R. Holton
  • Patent number: 11238916
    Abstract: A memory device including a memory unit and a control circuit is provided. The memory unit includes a plurality of memory banks. The memory banks are at least divided into a first group and a second group. The control circuit is coupled to the memory unit. The control circuit is configured to perform a first refresh operation on the first group and the second group. When the control circuit performs the first refresh operation on one of the first group and the second group, the control circuit performs a second refresh operation on a victim row of the other one of the first group and the second group. In addition, a method for refreshing a memory device is also provided.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: February 1, 2022
    Assignee: Winbond Electronics Corp.
    Inventor: Kan-Yuan Cheng
  • Patent number: 11222674
    Abstract: A memory device includes a top select cell, a top dummy cell and a string of memory cells. The top select cell has a first terminal coupled to a bit line and a control terminal coupled to a top select line. The top dummy cell has a control terminal coupled to a top dummy word line. The string of memory cells has control terminals coupled to respective word lines. A method operating the memory device includes prior to a program operation, applying a pre-pulse voltage to the top dummy word line, the top select line and the bit line while applying a low voltage to the word lines, and then sequentially applying the low voltage to the top dummy word line, the top select line and the bit line while applying the low voltage to the word lines.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 11, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Shan Li, Kaikai You, Ying Cui, Jianquan Jia, Kaiwei Li, An Zhang
  • Patent number: 11211113
    Abstract: Some embodiments include an integrated assembly having first and second wordlines coupled with DRIVER circuitry. The first wordline has a first end distal from the DRIVER circuitry, and the second wordline has a second end distal from the DRIVER circuitry. A switch is adjacent to the first end and is configured to couple said first end to one or both of the second end and a LOW-VOLTAGE-REFERENCE-SOURCE (e.g., a VNWL supply) during a transition of the first wordline from an “ON” state to an “OFF” state.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 11211112
    Abstract: A semiconductor device includes an internal column control signal generation circuit, a bank address transfer circuit, and a first bank control circuit. The internal column control signal generation circuit generates a column control signal to output an internal column control signal. The bank address transfer circuit receives a bank address to generate an inverted bank address and outputs the bank address and the inverted bank address. The first bank control circuit generates a first bank active signal based on at least one of the bank address and the inverted bank address and latches the first bank active signal based on the internal column control signal to generate a first bank column control signal.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: December 28, 2021
    Assignee: SK hynix Inc.
    Inventors: Geun Ho Choi, Kyung Mook Kim, Woongrae Kim