Abstract: The present invention provides a physical layer and associated signal processing method for clock domain transfer of quarter-rate data. In the embodiments of the present invention, the quarter-rate data is processed by many sampling circuits by using a first clock signal, a second clock signal and a third clock signal, and phases of these clock signals are aligned by using a training mechanism to that the clock signals have better timing margins.

Abstract: The present disclosure provides a storage unit, a data writing method and a data reading method thereof, a memory and an electronic device. The storage unit includes a semiconductor substrate, a first insulating medium layer, a ferroelectric thin film layer, a bottom electrode, a tunnel junction, a first metal interconnection portion, a second metal interconnection portion, a third metal interconnection portion and a fourth metal interconnection portion. The first insulating medium layer is formed on the semiconductor substrate, the ferroelectric thin film layer is disposed on the first insulating medium layer, the bottom electrode is formed on the ferroelectric thin film layer, and the tunnel junction is formed on the bottom electrode. The first metal interconnection portion is connected to a first end of the bottom electrode, and the third metal interconnection portion is connected to a second end of the bottom electrode.

Abstract: Methods, systems, and devices for dirty write on power off are described. In an example, the described techniques may include writing memory cells of a device according to one or more parameters (e.g., reset current amplitude), where each memory cell is associated with a storage element storing a value based on a material property associated with the storage element. Additionally, the described techniques may include identifying, after writing the memory cells, an indication of power down for the device and refreshing, before the power down of the device, a portion of the memory cells based on identifying the indication of the power down for the device. In some cases, refreshing includes modifying at least one of the one or more parameters for a write operation for the portion of the memory cells.

Abstract: A device includes an array of memory cells with a first word line coupled to at least a subset of the array of memory cells and control logic coupled to the first word line. The control logic to detect, within a queue, a first read command to read first data from a first page of the subset and a second read command to read second data from a second page of the subset. The control logic is further to cause a voltage applied to the first word line to move to a target value. The control logic is further to cause a page buffer to sense the first data from a first bit line coupled to the first page and to sense the second data from a second bit line coupled to the second page. The control logic is further to cause the first word line to be discharged.

Abstract: An apparatus having a power bus supplying power to a component of a memory device. The apparatus includes a noise source circuit generating a plurality of noise source signals that simulate a real-world noise. The apparatus can include a pulse generator circuit that receives the noise source signal and outputs at least one noise profile signal based on the noise source signal. A bus shorting circuit can be connected to the pulse generator circuit to receive the at least one noise profile signal. The bus shorting circuit can have at least one transistor connected between a first rail and a second rail of the power bus. Based on the at least one noise profile signal, the bus shorting circuit intermittently connects the at least one transistor between the first rail to the second rail to induce noise on the power bus.

Abstract: Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one another. A logic component is coupled to the plurality of memory components. At least one memory component comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component. Timing circuitry is coupled to the array and sensing circuitry and configured to control timing of operations for the sensing circuitry. The logic component comprises control logic coupled to the timing circuitry. The control logic is configured to execute instructions to cause the sensing circuitry to perform the operations.

Abstract: A memory device includes an array of memory cells, a plurality of bit lines, a current control circuit, and a discharge enable circuit. The array of memory cells includes a plurality of columns of memory cells. The plurality of bit lines are respectively coupled to the plurality of columns of memory cells. The current control circuit is coupled to the plurality of bit lines to control a discharge current in a discharge operation. The discharge enable circuit is coupled to the current control circuit to enable the discharge operation. The discharge operation discharges a charge on the plurality of bit lines.

Abstract: A resistive memory device includes word lines, first memory cells, second memory cells, bit lines, source lines, and a driver. The driver provides a forming voltage to the first memory cells and the second memory cells through the bit lines and the source lines in a forming process. A first connection length along the bit lines and the source lines between the first memory cells and the driver is longer than a second connection length along the bit lines and the source lines between the second memory cells and the driver. The forming process is performed to the first memory cells before the forming process is performed to the second memory cells. A first value of the forming voltage provided to the first memory cells is less than a second value of the forming voltage provided to the second memory cells.

Abstract: A block of dynamic memory in a DRAM device is organized to share a common set of bitlines may be erased/destroyed/randomized by concurrently activating multiple (or all) of the wordlines of the block. The data held in the sense amplifiers and cells of an active wordline may be erased by precharging the sense amplifiers and then writing precharge voltages into the cells of the open row. Rows are selectively configured to either be refreshed or not refreshed. The rows that are not refreshed will, after a time, lose their contents thereby reducing the time interval for attack. An external signal can cause the isolation of a memory device or module and initiation of automatic erasure of the memory contents of the device or module using one of the methods disclosed herein. The trigger for the external signal may be one or more of temperature changes/conditions, loss of power, and/or external commands from a controller.

Abstract: The disclosed technology relates to a non-volatile (NV) static random-access memory (SRAM) device, and to a method of operating the same. The NV-SRAM device includes a plurality of bit-cells, wherein each bit-cell comprises: an SRAM bit-cell; a first bit-line connected via a first access element to the SRAM bit-cell; a NV bit-cell connected via a switch to the SRAM bit-cell; and a second bit-line connected via a second access element to the NV bit-cell. The NV-SRAM device is configured to independently write data from the first bit-line into the SRAM bit-cell through the first access element, and respectively from the second bit-line into the NV bit-cell through the second access element.

Abstract: A memory device comprising multiple memory planes is disclosed. The memory device further comprises a first pump set coupled with the multiple memory planes, and configured to supply a first output voltage to multiple linear regulators during a steady phase, and a second pump set coupled with the multiple memory planes, and configured to supply a second output voltage to the multiple linear regulators during a ramping phase. The multiple linear regulators can includes a first linear regulator set configured to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of the plurality of memory planes, and a second linear regulator set configured to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of the plurality of memory planes.

Abstract: A power management circuit in a low-power double data rate memory is configured to manage a plurality of power supplies memory according to a reference voltage. A low dropout regulator has a first transmitting terminal and a second transmitting terminal. The low dropout regulator adjusts a voltage difference between a first voltage and a second voltage according to the reference voltage. A power network structure is electrically connected to the low dropout regulator. A first power network circuit has a first connecting point, a grid shape and a first unit network space. A second power network circuit has a second connecting point, another grid shape and a second unit network space. The second connecting point is separated from the first connecting point by a distance. The distance is smaller than or equal to one of the first unit network space and the second unit network space.

Abstract: A data writing method and a memory, in which the data writing method is used for writing data to a memory array of the memory. The data writing method includes that: old data is read from a target column of the memory array; the old data is updated according to data to be written which carries target data bits information to generate new data; and the new data is written into the target column, in which the memory includes a plurality of data columns, the data is required to be written into the target column, and the target column includes a part of the data columns.

Abstract: Provided are a control circuit and a delay circuit. The control circuit includes a control unit, a first feedback unit, and a second feedback unit. The first feedback unit outputs a first feedback signal according to a voltage of the control unit and a first reference voltage. The second feedback unit outputs a second feedback signal according to a voltage output by the first feedback unit and a second reference voltage. The control unit is configured to adjust a voltage of the second terminal of the control unit according to the first feedback signal and adjust a voltage of a third terminal of the control unit according to the second feedback signal, to make a change value, changing along with a first parameter, of a current of the control unit be within a first range.

Abstract: An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

Abstract: The present invention provides a semiconductor module, a semiconductor member, and a method for manufacturing the same that make it possible to improve heat dissipation efficiency. This semiconductor module 1 comprises: a power supply unit 40; a RAM unit 50, which is a RAM module having a facing surface disposed so as to face an exposed surface of a logic chip 20 and an exposed surface of the power supply unit 40, the RAM module being disposed across some of a plurality of logic chip signal terminals 22 and some of a plurality of power supply unit power supply terminals 41; and a support substrate 10 having a power feeding circuit capable of feeding electrical power to the logic chip and to the power supply unit 40, one main surface of the support substrate 10 being disposed adjacent to a heat dissipation surface of the RAM unit 50, which is the surface of the RAM unit 50 opposite the facing surface.

Abstract: A semiconductor device includes a cell circuit including a plurality of memory arrays, and a control circuit configured to control the cell circuit. A memory array of the plurality of memory arrays has a plurality of sub-arrays including a first sub-array and a second sub array, and an array connecting circuit configured to connect bit lines of the first sub-array to respective corresponding bit lines of the second sub-array according to a copy signal. The semiconductor device may further include a partial sum circuit configured to perform charge sharing between a plurality of bit lines of the first sub-array.

Abstract: A memory device is provided. The memory device includes at least one memory chip and a logic chip. Each of the at least one memory chip includes a memory array, a plurality of bit lines, and a plurality of data paths. The data paths respectively correspond to the bit lines. The number of the data paths is equal to or less than the number of the bit lines. A plurality of data transmission ports of the logic chip are electrically connected to the data paths of the at least one memory chip in a one-to-one manner. The number of the data transmission ports is equal to a sum of the data paths of the at least one memory chip.

Abstract: A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.