Abstract: Systems, apparatus and methods are provided for performing program operations in a non-volatile storage system. In one embodiment, there is provided a method that may comprise categorizing active storage blocks of a non-volatile storage device into a robust group and a less-robust group based on a number of factors including page error count, program time and number of Program/Erase (P/E) cycles; determining that a cache program operation needs to be performed; selecting a first storage block from the robust group to perform the cache program operation; determining that a regular program operation needs to be performed; and selecting a second storage block from the less-robust group to perform the regular program operation.

Abstract: Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.

Abstract: An antifuse circuit includes a current generator and an antifuse sense unit. The current generator has at least one electronic device. The antifuse sense unit is electrically connected to the current generator, and the antifuse sense unit has at least one copied electronic device. An electronic device specification of the at least one electronic device of the antifuse sense unit is equal to an electronic device specification of the at least one copied electronic device of the current generator. The current generator supplies a current to the antifuse sense unit that senses an antifuse.

Abstract: A dynamic memory array of a DRAM device is operated using a bitline voltage that is greater than the operating (i.e., switching) voltage of a majority of the digital logic circuitry of the DRAM device. The digital logic circuitry is operated using a supply voltage that is lower than the voltage used to store/retrieve data on the bitlines of the DRAM array. This allows lower voltage swing (and thus lower power) digital logic to be used for a majority of the non-storage array logic on the DRAM device—thus reducing the power consumption of the non-storage array logic which, in turn, reduces the power consumption of the DRAM device as a whole.

Abstract: Devices are disclosed. A device may include a source configured to couple to a number of memory cells. The device may also include at least one transistor coupled between the source and a ground voltage. Further, the device may include an antifuse coupled between the at least one transistor and the ground voltage. Methods and systems are also disclosed.

Abstract: Systems and methods for gating, via clock gating circuitry, a clock signal based at least in part on a mode register value indicative of synchronization of a command address signal with the clock signal when the mode register value indicates synchronization of the command address signal with the clock signal has not occurred. The clock gating circuitry is configured to, gate the clock signal based at least in part on the mode register value and a chip select signal value when the mode register value indicates synchronization of the command address signal with the clock signal has occurred.

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

Abstract: A method for determining a sense boundary of a sense amplifier includes: writing first data into a memory array; reading the first data in a first memory cell of the memory array, and reversely writing second data into the first memory cell; reading, after a preset row precharge time, the first data in a second memory cell on a bit line where the first memory cell is located; and reversely writing the second data into the second memory cell when the first data is read in the second memory cell.

Abstract: An apparatus may include a refresh control circuit with multiple timing circuits. The timing circuits may be used to control steal rates, e.g., the rate of refresh time slots dedicated to healing victim word lines of row hammers. The timing circuits may be controlled to allow independent adjustment of the steal rates for different victim word lines. Thus, different victim word lines may be refreshed at different rates and the different rates may be independent of one another.

Abstract: A magnetic domain wall displacement element includes a first ferromagnetic layer, a second ferromagnetic layer extending in a second direction and magnetically recordable, a nonmagnetic layer, and a first conductive part having a first intermediate layer and a second conductive part having a second intermediate layer, in which the first intermediate layer is sandwiched between first and second magnetization regions and exhibiting first and second magnetization directions, the second intermediate layer is sandwiched between a third magnetization region and exhibiting the second magnetization direction and a fourth magnetization region exhibiting the first magnetization direction in the first direction, and an area of the first magnetization region is larger than an area of the second magnetization region and an area of the third magnetization region is smaller than an area of the fourth magnetization region in a cross section in the first direction and the second direction.

Abstract: Disclosed herein is an apparatus that includes: a driver circuit configured to operate on a power voltage supplied from an internal power supply line; a first external power supply line supplied with a first external power voltage; a second external power supply line supplied with a second external power voltage; a plurality of first switch circuits coupled between the first external power supply line and the internal power supply line, the plurality of first switch circuits being arranged on a plurality of first circuit areas; and a plurality of second switch circuits coupled between the second external power supply line and the internal power supply line, the plurality of second switch circuits being arranged on a plurality of second circuit areas. The plurality of first circuit areas and the plurality of second circuit areas are arranged in a first direction in a predetermined order.

Abstract: According to one embodiment, a semiconductor memory device includes a first bit line extending in a first direction and coupled to a first memory cell, a first pad coupled to the first bit line, a first sense amplifier coupled to the first pad, a second bit line being adjacent to the first bit line and extending in the first direction and coupled to a second memory cell, a second pad coupled to the second bit line, and a second sense amplifier coupled to the second pad. The first and second sense amplifiers are adjacent to each other and are arranged in a second direction intersecting the first direction. The first and second pads are adjacent to each other and are arranged in a third direction intersecting the first direction and the second direction.

Abstract: A semiconductor memory device includes a memory cell that includes a capacitor including a first and second end and a first transistor. The first transistor includes a third and fourth end, is coupled to the first end at the fourth end, and contains an oxide semiconductor. A bit line is coupled to the third end. A sense amplifier is coupled to the bit line and coupled between a first node of a first potential and a second node of a second potential lower than the first potential. A potential generator is configured to supply the second end with a fourth potential that is different from a third potential intermediate between the first potential and the second potential.

Abstract: The present invention discloses a memory device and operation method thereof. The operation method comprises: programming a plurality of first strings of a plurality of string pairs representing a finite state machine (FSM) to an in-memory-searching (IMS) array of a memory device; programming a plurality of second strings of the string pairs to a working memory of the memory device; and programming a string representing a starting state of the FSM to a buffer of the memory device.

Abstract: Disclosed are embodiments of a low-leakage row decoder and a memory circuit incorporating the row decoder. The row decoder includes wordline driver circuitry including first devices (pre-drivers) and second devices (wordline drivers). Each second device is connected in series between a first device and a wordline for a row in a memory array. The first devices can be directly connected to a positive supply voltage rail and connected to a ground rail through a footer. The second devices can be connected to the positive supply voltage rail through a header and directly connected to the ground rail. The on/off states of the header and footer are controlled by clock signal-dependent control signals so that they are either concurrently on or off. With this configuration, leakage power consumption of the wordline driver circuitry is minimized while the memory structures as idle and also while it operates in a normal active mode.

Abstract: A memory device is disclosed. The memory device includes a plurality of memory cells arranged in a plurality of rows and a plurality of columns; a plurality of word lines, each of the word lines coupled to a corresponding row of the memory cells; a plurality of bit lines, each of the bit lines coupled to a corresponding column of the memory cells; and a plurality of second word lines, each of the second word lines coupled to a corresponding column of the memory cells.

Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

Abstract: A semiconductor device includes a first switch coupling a first switch coupling a first power source and a first node according to a first control signal; a sense amplifier coupled between the first node and a second node and performing a sensing operation; a second switch coupling a second power source and the second node according to a second control signal; and a sense amplifier control circuit providing the first control signal and the second control signal. The sense amplifier control circuit controls the second control signal so that a voltage of the second node reaches a shift voltage higher than a voltage of the second power source during a first sensing period of the sensing operation and a bias current flows through the second node during a second sensing period of the sensing operation. The sensing period is subsequent to the first sensing period.

Abstract: An in-memory processing apparatus includes: a memory cell array comprising memory cell groups configured to generate current sums of column currents flowing through respective column lines in response to input signals input through row lines; voltage controlled delay circuits configured to output, in response to an input of a start signal at a first time point, stop signals at second time points delayed by delay times determined based on magnitudes of applied sampling voltages corresponding to the current sums; a time-digital converter configured to perform time-digital conversion at the second time points; and sampling resistors connected to the column lines, wherein the time-digital converter is configured to reset a counter at the first time point, and output counting values as digital values at the second time points.

Abstract: Page data can be propagated sequentially from a section to the neighboring section, and from this section to subsequent section adjacent to it until a page register set is reached. In a described apparatus based on this page-data-copy scheme, access data from a page register (which is also used for storing the data accessed using the page-data-copy scheme) with a conditional read-access method in conjunction with an arithmetic unit can execute the arithmetic process of an AI system.