Abstract: A circuit is provided to make the propagation delay time of each signal path substantially the same without using a low resistance process even when wiring lengths are different. In the circuit, output nodes a to d are individually disposed at the output side of transmission gates TG2, TG4, TG6, and TG8, these output nodes a to d are connected so as to have an equal wiring length, inverters IV11 and IV12 are disposed at the output nodes a and d, and a common node e is disposed at a position where the wiring length from each of the inverters IV11 and IV12 becomes identical.

Abstract: An output buffer includes a pair of main complimentary MOS transistors connected to at least one additional pair of complementary MOS transistors connected in parallel to the pair of main transistors by means of a pair of switches controlled by a numeric word for activating or not activating the additional pair of transistors. A control circuit delivers the numeric word which represents the conductivity of the pair of main transistors included in the output buffer. The additional transistors are sized in such a way that when they are activated, the equivalent impedance of the output buffer is approximately constant.

Abstract: A first voltage conversion circuit converts first and second reference input voltages into first and second differential output voltage. A second voltage conversion circuit converts the first reference input voltage and a control input voltage into a third differential output voltage. The third differential output voltage is inputted to an exponential conversion element. The first and second differential output voltages are inputted to an active impedance bridge. The active impedance bridge outputs a gain control voltage of the first and second voltage conversion circuits. A balanced condition of the active impedance bridge determines the exponential conversion characteristic of the output current to the control input voltage of the exponential conversion element.

Abstract: Circuits, methods, and apparatus for using redundant circuitry on integrated circuits in order to increase manufacturing yields. One exemplary embodiment of the present invention provides a circuit configuration wherein functional circuit blocks in a group of circuit blocks are selected by multiplexers. Multiplexers at the input and output of the group of circuit blocks steer input and output signals to and from functional circuit blocks, avoiding circuit blocks found to be defective or nonfunctional. Multiple groups of these circuit blocks may be arranged in series and in parallel. Alternate multiplexer configurations may be used in order to provide a higher level of redundancy. Other embodiments use all functional circuit blocks and sort integrated circuits based on the level of functionality or performance. Other embodiments provide methods of testing integrated circuits having one or more of these circuit configurations.

Abstract: A source follower capable of compensating the threshold voltage is provided. The source follower comprises a current source, a switching circuit, and a thin film transistor. The source follower makes the threshold voltage of the thin film transistor constant by using the current source, and makes the input voltage nearly equal to the output voltage by using the storage capacitor and the compensating capacitor. Thus, it can make the error of the output voltage fall in the error range of the gray level voltage.

Abstract: A circuit arrangement is provided for actuating a semiconductor switch connected in series with an inductive load. The circuit includes a first input terminal for supplying an input signal which governs whether the semiconductor switch is on or off, a second input terminal for supplying a voltage measurement signal, and an output terminal for providing an actuation signal for the semiconductor switch. Connected between the first input terminal and the output terminal is a driver circuit which, for a given level of the input signal, takes a control signal as a basis for generating an actuation signal having a first or a second signal profile.

Abstract: An apparatus and a method to control an output signal from a DAC-driven amplifier-based driver are disclosed. The apparatus includes an amplifier and a driver. The amplifier has a negative input terminal, a positive input terminal, and a first output terminal. The driver has an input terminal and a second output terminal, the input terminal coupled to the first output terminal of the amplifier and the second output terminal coupled to the positive input terminal of the amplifier to provide a positive feedback to the amplifier.

Abstract: A method of switching the mode of a PLL circuit which has a high-speed mode and a normal mode, which allows the PLL circuit to be locked up at a high speed. The PLL circuit includes a phase comparator and a charge pump for generating a current depending on a comparison output signal from the phase comparator. The mode switching method includes the steps of detecting whether a current output terminal of the charge pump is in a high impedance state, and switching the mode of the PLL circuit from the high-speed mode to the normal mode or from the normal mode to the high-speed mode when the high impedance state is detected.

Abstract: An apparatus and method for regenerating reset and clock signals and a high-speed digital system using the apparatus and method are provided. In the regenerating circuit of the invention, a clock circuit receives an external clock signal and generates there from an internal clock signal, which is forwarded to a plurality of clocked circuits such as, for example, D flip-flops. A reset circuit receives an external reset signal and generates therefrom an internal reset signal, which is forwarded to the clocked circuits to reset the clock circuits. A clock masking circuit masks the internal clock signal for a masking period such that the clocked circuits are not clocked during the masking period. The high-speed digital system of the invention includes a plurality of function blocks coupled on a bus. The reset and clock regenerating circuit of the invention generates internal reset and clock signals from externally applied reset and clock signals.

Abstract: A current to voltage conversion circuit for improving the speed of a photoelectric conversion device and frequency characteristics of an amplifier by improving a method for switching the gain of an amplification circuit for a photo detector integrated circuit (PDIC). Photocurrent generated in the photoelectric conversion device, such as a photodiode, is transferred to the amplifier by means of current mirroring, so as to raise a bias voltage to the photoelectric conversion device and enhance a response speed thereof. Further, the amount of current generated in the photoelectric conversion device is adjusted through control of a resistance ratio of a current mirror circuit. Therefore, a fixed feedback resistor can be used for the amplifier irrespective of modes, so as to enhance frequency characteristics of the amplifier.

Abstract: A clocked-scan flip-flop for multi-threshold CMOS (MTCMOS) is provided. The clocked-scan flip-flop includes a first switching unit which switches normal data that are input from the outside and outputs the data; a second switching unit which switches scan data that are input from the outside and outputs the data; a latch unit which latches the data input from the first switching unit or the second switching unit; and a clock input unit which controls the switching operations of the first and second switching units according to the result of a predetermined operation on a clock signal and a scan clock signal that are input from the outside. The clocked-scan flip-flop has the characteristics of a complementary pass-transistor (CP) flip-flop, that is, low power consumption and high performance. Also, the clocked-scan flip-flop provides a full-scale scan function for test purposes.

Abstract: The respective ends of input wiring on a printed wiring board of a signal transmission circuit are connected to an input terminal section and a transistor. One terminal of a first capacitor and a first resistor are respectively connected to the input wiring. A leading-side transmission path from a connection point with the first capacitor to a connection point with the input terminal section is formed by only a conductive pattern. An intermediate transmission path from the connection point with the first capacitor to a connection point with the first resistor includes two or more through holes or via holes. The intermediate transmission path is placed near grounding wiring on the printed wiring board. When one terminal of a second capacitor is connected to the intermediate transmission path, a transmission path between the respective connection points with the two capacitors includes one or more through holes or via holes.

Abstract: Power supply voltages are selectively modulated to correspond with degraded input voltages to a logic device. Modulated power supply voltages are provided to transistors within the logic device, so that the degraded input voltages supplied to the transistors are sufficient to turn the transistors substantially on or off. Leakage currents are prevented thereby from flowing across the transistors.

Abstract: A power switching circuit including an MOS power switching transistor (P1) is disclosed. The power switching transistor (P1) has a body node that is selectably biased to either its source or its drain, depending upon a comparison of the voltage at the circuit input (IN) relative to the voltage at the circuit output (OUT). In a reverse voltage situation in which the output voltage exceeds the input voltage, a first body node switching transistor (P11) connected between the body node of the power switching transistor (P1) and its source is turned off by a voltage corresponding to the output voltage, as conducted from the drain of the power switching transistor (P1) through a pull-down device (P5) in an inverter.

Abstract: The present invention comprises an integral triangular voltage waveform generator (170, 180) and triangular to pseudo-sinusoidal current waveform converter (170, 180). The outputs of the present invention are preferably differential (130, 131), although the invention can easily be modified for single ended output. The frequency of the output waveforms corresponds to the frequency of the input reference clock.

Abstract: A robust output buffer component capable of providing high quality output signals comprising a cascode module for receiving a differential signal from a differential pair module and transmitting that differential signal as two output waveforms. Using a bipolar implementation example, the emitter end of a common base cascode pair is coupled to the collector end of a common emitter differential pair with an optional resistive module inserted between the cascode pair and the differential pair. Engineering the cascode bias, the resistance at the collector nodes of the differential pair and/or the resistance at the base nodes of the differential pair effects: the degree of non-linearity of the base-collector capacitance as a function of the base-collector voltage, the voltage swing of the collector nodes, and the degree of symmetry of the input voltages. These three parameters may be used to optimize the symmetry of the output waveforms.

Abstract: A non-integer order controller for providing stability in a circuit. The non-integer order controller may be in either a feed-forward path or a feedback path of the circuit. Thus, the non-integer order controller is operable to provide stability for the circuit. The closed loop system may be a phase lock loop.

Abstract: A method for amplifying a digital signal representative of data to be transmitted by a line driver with pre-emphasis over an output line is provided. The gain of the line driver is varied between an upper value to coincide with switching of the digital signal and a lower value in absence of the digital signal switching. In particular, the varying includes amplifying the digital signal with a first gain for generating an amplified digital signal, delaying the digital signal with a predetermined delay for generating a delayed digital signal, and amplifying the delayed digital signal with a second gain for generating a delayed and amplified digital signal. An ouput signal corresponding to a difference between the amplified digital signal and the delayed and amplified digital signal is output over the output line.

Abstract: Charging a storage cell requires the electromotive force exerted at a photogenerating cell in addition to the voltage equal to or higher than the forward on voltage developed at an backflow preventing diode. Therefore, the charging is inefficient. Moreover, the area of the backflow preventing diode must be large in consideration for a current supply from the photogenerating cell at a high intensity of illumination. A charging circuit, constructed using a differential amplifier, which has a power supply therefor separated from another power supply, is used as a direction-of-current detecting circuit that detects the direction of current from a voltage difference between two different power supplies. Consequently, a switch is logically turned on or off depending on whether charging or non-charging is under way. Thus, on voltage to be developed during charging is lowered. Moreover, the size or area of a transistor that acts as a logical circuit is made smaller than that of the backflow preventing diode.

Abstract: A latch device is provided having a latch mode and a transparent mode. In the latch mode, the latch device synchronizes a data signal to a clock signal. In the transparent mode, the data signal drives the output without clock synchronization, such that the clock input signal is unused. The latch device can be employed in an optical driver for optical network laser diodes.