Abstract: A variable delay circuit uses a plurality of inverters or inverting gates as delay elements in a delay line. In one embodiment of the invention, the point in the delay circuit at which an input clock signal enters the delay circuit is adjusted to vary the delay of an output clock signal. In another embodiment, the point in the delay circuit from which the output clock signal exits the delay circuit is adjusted to vary the delay of an output clock signal. In either case, the polarity of the input or output clock signal is adjusted as the delay is adjusted so there are always an even number of inverters or inverting gates between an input terminal to which the input clock signal is applied and an output terminal from which the output clock signal is generated.

Abstract: A differential charge pump circuit for eliminating influence of mismatches between current sources is disclosed. The differential charge pump circuit includes a floating capacitor for providing an output voltage, a slicer for outputting a comparison signal to control a charge/discharge actions of the floating capacitor, a first current source, a second current source, a first-common-mode current source, a second-common-mode current source, and a third-common-mode current source connected in parallel with the first current source. The differential charge pump circuit of the present invention utilizes switches to switch the charge and discharge current paths of the capacitor with respect to the common mode current source and the charge/discharge current source. Therefore, the duty cycle of the output signal is free from being adversely influenced by the mismatches between the current sources.

Abstract: A capacitive charge pump that can be implemented in such devices as e.g. a phase locked loop (PLL). The charge pump includes at least one capacitor in the charge path and discharge path for limiting the amount of charge provided to or removed from a filter capacitor of a PLL. In one example, a second capacitor may be provided in the charge path or discharge path to reduce the capacitance (if provided in series) or increase the capacitance (if provided in parallel) to adjust the maximum amount of charge transferred to a filter capacitor. In one example, multiple capacitive stages may be implemented in parallel to increase the maximum amount of charge transferred to a filter capacitor. Each stage is enabled after a delayed period of time from when the previous stage was enabled.

Abstract: A drive circuit for LEDs or other light-emitting elements with which the influence of the changes in temperature or power supply voltage and the element variations can be restrained in order to output a pulse current with a constant level. When n-type MOS transistor 10 is on, power is supplied from switching power supply 60 to the LED, and the current of LED is detected by resistor 20. The error signal Serr between said detection signal Sfb and setpoint signal Sref is generated by error signal generating unit 30 and is averaged by signal holding unit 40. The power supplied to the LED is controlled corresponding to the averaged error signal SerrA. When n-type MOS transistor 10 is turned off from the on state, the power supplied to the LED is stopped, and error signal SerrA is held in signal holding unit 40. When n-type MOS transistor 10 is turned on from the off state, the averaging of error signal Serr is started with the signal level of the held error signal SerrA used as the initial level.

Abstract: The present invention discloses a digital control logic circuit having a characteristic of time hysteresis for controlling transition of a digital control signal for a predetermined period, comprising a first time hysteresis unit, a second time hysteresis unit and an inverter. The first time has the characteristic of time hysteresis when an input signal transits from a first level to a second level. The second time hysteresis unit has the characteristic of time hysteresis connected to the first hysteresis in series when the input signal transits from the second level to the first level.

Abstract: Circuits and methods are provided for clock adjustment. A method for clock adjustment includes receiving feedback clocks from independent ASIC modules. The method includes comparing the feedback clocks to a reference clock to generate phase measurement values. A common delay is removed from the phase measurement values to form normalized correction values. Target phase values and clock select values are selected using the normalized correction values. And, clock signals to independent ASIC modules are adjusted based on the target phase values and clock select values.

Abstract: Provided is a system for implementing gain control in an amplification module comprising a first stage amplifier having a number of first stage input and output ports. The first stage amplifier is configured to provide first stage amplification to a received input signal and produce from the amplified input signal a number of output signals. Also included are a number of second stage amplifiers, each having second stage input and output ports, the second stage input ports being respectively coupled to the first stage output ports and being configured to receive the number of output signals. A gain control device is coupled to at least one from the group including the first stage input ports, the first stage output ports, and the second stage output ports. The gain control device is also configured to control a gain of at least one of the first stage amplifier and one or more of the number of second stage amplifiers.

Abstract: A pulse-width controller (1800) is described. Pulse generators (1700L, 1700H) are coupled to receive clock signals (1320, 1321) and configured to extend respective high-time and low-time pulse widths to provide signals with lengthened pulse widths (1320P, 1321P). Control signals (1803, 1804) are generated from pulse-width lengthened signals (1320P, 1321P). Clock signals (1320, 1321) and the pulse-width lengthened signals (1320PB, 1321P, 1321PB) are provided to differential logic (1823 through 1828), such as Differential Cascode Voltage Switch Logic, to provide a differential output (1611, 1612) which is duty-cycle adjusted. The control signals (1803, 1804) in combination with the pulse-width lengthened signals (1320PB, 1321P, 1321PB) are used to selectively activate a respective portion of the differential logic (1823 through 1828) to pass signals to the differential output (1611, 1612).

Abstract: A charge/discharge current detection circuit includes a detection resistance that converts a charge current and a discharge current to a detection voltage, a level shifter circuit that level-shifts the detection voltage by a predetermined value, and an amplifier circuit that amplifies an output voltage of the level shifter circuit and outputs the amplified output voltage of the level shifter circuit. The level shifter circuit applies to the detection voltage a predetermined divided voltage obtained by resistance-dividing a reference voltage, to thereby level-shift the detection voltage.

Abstract: Embodiments of the present invention provide for generating a sampled differential pattern signal with reduced jitter. In one embodiment of the present invention, a seed frequency generator provides a differential seed frequency signal. The differential seed frequency signal is converted to a single ended seed frequency signal by a differential-to-single ended converter. The pattern generation logic utilizes the single ended seed frequency signal to generate single ended pattern signals. Single ended-to-differential samplers then generate a sampled differential pattern signal by sampling the single ended pattern signal according to the differential seed frequency signal.

Abstract: A signal power detector includes an input coupling circuit and a rectifying operational amplifier. The input coupling circuit is operably coupled to receive a signal and to convert the signal into a first input and a rectifying input. The rectifying operational amplifier is operably coupled to receive the first input and the rectifying input and to produce therefrom a rectified output signal that represents a peak of the received signal.

Abstract: A line driver with programmable slew rates is disclosed. The line driver can be configured to have a slew rate based on a desired fraction of the clock period of the system clock. Specifically, the clock period of the system clock signal is equal to a clock period reference number multiplied by a base delay. A number of base delays is calculated to be equal to the desired fraction of the clock period multiplied by the clock period reference number. The slew rate of the line driver is adjusted to be equal to the number of base delays.

Abstract: The invention relates to electronic “sample and hold” circuits and, in particular, to such circuits which may implemented in integrated form. A method and circuit are provided for improving isolation during the hold mode of operation of a sampling circuit. An input differential signal is provided to parallel circuit paths (viz. a primary sampling path and an isolation path) which are identical (electronically equivalent) and, therefore, provide the same impedance leading to hold capacitor(s). The circuit paths are configured, relative to the differential inputs, so that any feed through (leakage) of the differential input signal is subtracted (cancelled) during the hold mode.

Abstract: One end of a control signal line having a buffer is connected to a control terminal. The other end of the control signal line is connected to a third terminal of an input/output logic changing circuit, a gate of a PMOSFET, and a gate of an NMOSFET. An input terminal is connected to a first terminal of the logic changing circuit. A second terminal of the logic changing circuit is connected to an output terminal. These elements are provided on a semiconductor chip. When the input terminal is in an open state, the PMOSFET and the NMOSFET functioning as pull-up and pull-down MOS transistors, respectively, are controlled by a control signal on the control signal line. When an input signal is applied to the input terminal, the logic changing circuit determines a logic level of an output signal based on the input signal and the control signal to thereby output the output signal to the output terminal.

Abstract: A driver stage uses a primary driver and a secondary driver to balance drive current when transmitting a new data bit different than bits consecutively transmitted immediately previous to the new data bit. The primary driver activates one of a pull-down device and a pull-up device whenever transmitting a data bit. The secondary driver activates one of its pull-down device and a pull-up device when two or more consecutive are detected to be transmitted. In this case, current flow of the driver stage induced by the first of the consecutive bits is reduced by the secondary driver.

Abstract: A transconductance control circuit includes a master device having first and second field effect devices coupled to respective first and second current sources, a reference device coupled to a third current source, and comparison circuitry. The comparison circuitry includes at least first, second and third inputs and at least one output, with the first input configured to receive a reference signal associated with the reference device, the second and third inputs coupled to respective terminals of the first and second field effect devices, and the output coupled to current control inputs of one or more of the current sources. The transconductance control circuit provides a feedback control arrangement in which, for example, the comparison circuitry output is utilized to adjust one or more of the current sources such that a difference signal Vg between voltages at the respective terminals of the first and second field effect devices converges to a reference signal VR.

Abstract: A transconductance-setting circuit (10, 20) and method. The circuit (10, 20) includes a first transconductor (14) coupled to a reference voltage (Vref) adapted to produce a current output (Ibias). A reference current source (Iref) is coupled to the first, transconductor (14), and a feedback loop (16) is coupled to the first transconductor (14) and the reference current source (Iref). The feedback loop (16) is adapted to reduce error in the current output (2i) and set the transconductance gm of the first transconductor (14) to a value proportional to the ratio of the reference current and the reference voltage. An auxiliary transconductor (22) is coupleable to the first transconductor (14), and control circuitry (30, 40) is adapted to control the coupling of the auxiliary transconductor (22) to the first transconductor (14) based on the current output (2i).

Abstract: A power reduction device which includes a first clocking device for generating a first clocking signal, a second clocking device for generating a second clocking signal, a synchronizer device for receiving the first and second clocking signals and being responsive to a first select signal and to a second control signal wherein upon receipt of either of the select or control signals, the synchronizing device generating a synchronized signal without a glitch therefrom wherein the synchronized signal corresponding to either the first or second clocking signals.

Abstract: A switch controlling circuit for the testing and fine-tuning of integrated circuits comprising of a series of flip-flops chain together in a serial manner. The contents of the flip-flop are shift in from the input of the first flip-flop in the chain. The output of each flip-flop connects to individual switch whereby the states of the flip-flops control the state of the switches.

Abstract: Two groups of diodes are connected to internal lines transmitting complementary signals, respectively, and positions of the centers of gravity of the groups of diodes are made coincident with each other. A circuit capable of preventing the deviation of the characteristics of differential transistor pair caused by an antenna effect and highly immune against a substrate noise can be achieved.