Abstract: A circuit including a differential sense circuit and a latch, the differential sense circuit and the latch coupled so as to form a differential sense latch such that, in operation, an electronic signal stored in the latch is retained for at least one clock cycle.

Abstract: The present invention relates to a circuitry for impedance matching. The invention utilizes circuitry for impedance matching, which circuitry for example is connected to a differential or balanced power amplifier or some other device in need of output impedance tuning. The circuitry includes at least one inductance connected to at least one device which conducts when being forward biased, and a direct current (DC) source controlling the conduction of the device. The circuitry eliminates the DC component of a signal passing through it. By controlling the device that is conducting when it is forward biased, it is possible to turn the circuitry on and off, thus altering the impedance at the output of the amplifier. Hence, a load switch has been created at the output of the amplifier.

Abstract: A control slew rate output driver has a plurality of component drivers that are switched on in turn to provide an edge on the output. A control circuit provides a series of respective control signals component drivers, which are correspondingly switched on in turn. The control circuit takes a signal, preferably a data signal, and supplies it in parallel to a plurality of delay buffers, which delay the data signal by different amounts to produce the control signals for the component drivers. The delay buffers are voltage controlled and the control voltage for each is provided by a respective tap of a voltage divider. The current passes through the voltage divider can be changed to change the control voltages and, hence, the overall rise or fall time provided by the output driver.

Abstract: An input circuit has hysteresis to mitigate the effects of input noise. The input circuit receives an analog input signal and determines whether the unregulated analog input signal is a high or a low voltage. The input circuit outputs a regulated low voltage (i.e., “0”) for a low input signal, and outputs a regulated high voltage (i.e., “1”) for a high input signal. The low-to-high transition occurs at a higher voltage than a high-to-low transition, which mitigates noise on the input signal. Furthermore, the comparator includes a feedback path from an output of the comparator to an input of the comparator. The feedback path causes some delay in any output voltage transition (i.e. high-to-low output transition or low-to-high transition), which further enhances the hystersis effect and improves noise immunity. An embodiment of the circuit interfaces with high voltage (e.g., 5V) input signals and outputs low voltage (e.g., 1.2V) output signals.

Abstract: A peak hold circuit which improves the precision of a hold voltage. The peak hold circuit includes a first input transistor which receives an input voltage and a second input transistor which receives the hold voltage. The peak hold circuit further includes a hold capacitor, a hold-voltage setting transistor and a bypass circuit. The hold capacitor supplies the hold voltage to the second input transistor. The hold-voltage setting transistor receives base current from the collector of the first input transistor and makes the hold voltage coincide with the input voltage in accordance with the base current. The bypass circuit bypasses bias current to be supplied to the second input transistor when the hold-voltage setting transistor is turned off.

Abstract: An apparatus for generated impedance matched output signals for an integrated circuit is disclosed. The apparatus includes a master true driver circuit, a master complement driver circuit and multiple clone output driver circuits. The master true driver circuit includes a first driver control, a first output driver, a first impedance matching resistor and a first load. The master complement driver circuit includes a second driver control, a second output driver, a second impedance matching resistor and a second load. The clone output driver circuits, which are substantially identical to each other, can produce impedance matched output signals to their respective substantially identical loads. Each of the clone output driver circuit includes a driver control, a first unity gain amplifier, a second unity gain amplifier and a load. The inputs to the first and second unity gain amplifiers are supplied by the master true circuit and the master complement circuit via the driver control.

Abstract: A complement reset multiplexer latch is provided. The complement reset multiplexer latch selectively regenerates a first or a second data input signal on an output node. To react to rising edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a second rising edge pulse reset control. To react to falling edges of the first or the second data signal, the complement reset multiplexer latch includes a first and a second falling edge pulse reset control. The complement reset multiplexer latch also selectively holds the output node at a stored value responsive to a clock signal. A multiplexer is used to select from the first or the second data input the value that is stored.

Abstract: A circuit to generate antipodal PSK signal and a correlator circuit for recovering information from PSK (phase shift keying) UWB transmissions includes providing a circuit component characterized by a transfer function having alternating stable and unstable regions. By setting the operating point in a stable region or an unstable region, a non-oscillatory or an oscillatory output signal can be produced.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more first control signals in response to (i) a clock signal and (ii) one or more second control signals. The second circuit may be (i) coupled to the first circuit via one or more path circuits and (ii) configured to present an output signal in response to the one or more first control signals. All of the one or more first control signals may have a preferred edge skew.

Abstract: An error amplifier circuit includes a differential amplifier with a cascode gain stage and an amplifier. The differential amplifier receives a first input signal and a second input signal and generates an output signal on an output terminal indicative of the difference between the first input signal and the second input signal. The cascode gain stage is coupled to receive the output signal of the differential amplifier and generates a second output signal. The cascode gain stage is biased by a bias current generated by a current mirror. The amplifier receives the second output signal from the cascode gain stage and generates a third output signal. The cascode gain stage is biased by a control signal for causing said current mirror to generate a bias current having substantially constant magnitude over variations in voltage differences of the first input signal and the second input signal.

Abstract: An impedance adjustment circuit generates an internal impedance adjustment signal and an impedance adjustment entry signal based on an externally applied impedance control signal. A data processing circuit decodes the internal impedance adjustment signal in synchronization with an internal clock signal to generate an output buffer drive signal of 5 bits. When the output buffer drive signal is applied to an output circuit of the succeeding stage as well as to an output replica circuit in a DLL circuit, the impedance of the output replica circuit is adjusted following adjustment of the output impedance.

Abstract: A voltage-controlled oscillation (VCO) circuit includes a current generator, a variable capacitor having a capacitance value which changes in accordance with a tuning voltage, an inductor which is electrically connected to the variable capacitor in parallel, and a fixed, capacitor which is electrically connected to the variable capacitor in parallel. The variable capacitor is electrically connected to the current generator in series.

Abstract: A family of emitter turn-off thyristors and their drive circuit comprise a gate turn-on (GTO) thyristor, a first switch, the drain of the first switch being connected to the cathode of the GTO thyristor, and a second switch connected between the gate of the GTO thyristor and the source of the first switch. The first switch consists of many paralleled metal oxide semiconductor field effect transistors (MOSFETs). The anode of the GTO thyristor and the source of the first switch serve as the annode and the cathode, respective, of the emitter turn-off thyristor. The emitter turn-off thyristor has four control electrodes: the gate of the GTO thyristor, the control electrode of the second switch, the gate of the first switch, and the cathode of the GTO thyristor. The drive circuit comprises a current source circuit, a voltage clamp circuit, a current direction detector, and a control circuit. The ETO thyristor further comprises a current sensing and over-current detector circuit.

Abstract: A frequency comparator detects the phase of a data signal DATA by using four-phase clocks ICLK, /ICLK, QCLK and /QCLK as a reference and detects a change in the phase. A counting processing unit counts a period in which a control signal UP2 or DN2 is activated within a predetermined period, and outputs an overflow detection signal LOL2 if the frequency is high. A hysteresis generating unit changes a signal LOL to the L level only after signal LOL goes low X times consecutively. On the other hand, after signal LOL is set to the L level once, the hysteresis generating unit changes signal LOL to the H level only after signal LOL2 goes high X times consecutively. With such a configuration, a phase-locked state detecting circuit with reduced malfunction even when a data signal having larger jitter is input can be provided.

Abstract: A clock generating circuit and method thereof is provided. The frequency ratio between the output clock and the system clock is calculated as that the first preset value divides by the second preset value. A data value is stored into a register. The sum of the data value and the first preset value is calculated as a first result by the first adder. The sum of the first result and the second preset value is calculated as a second result by the second adder. A multiplexer (MUX) is used to select the data value that should be stored into the register at next system clock from the first result and the second result according to the level of the output clock. The first result is compared with a reference value by the first comparator to generate the output clock, so that the frequency of the output clock can be changed arbitrarily and it is not required to redesign the circuit.

Abstract: A transconductor for generating a current corresponding to an input voltage. The transconductor has a crossing pairs structure. The transconductor comprises a first and a second MOS (Metal-Oxide Semiconductor) transistors mutually connected in series to a voltage source. A first bipolar transistor is connected to a current source. A collector terminal of the first bipolar terminal is connected to an output current terminal. An emitter terminal of the first bipolar terminal is connected to a gate terminal of the second MOS transistor. A second bipolar transistor is connected in series to the first bipolar transistor. A base terminal of the second bipolar transistor is connected to a node between the first MOS transistor and the second MOS transistor. A third MOS transistor is provided. A gate terminal of the third MOS transistor is connected to an input terminal for a signal from outside. A drain terminal of the third MOS transistor is connected to an emitter terminal of the second bipolar transistor.

Abstract: In a clock shaping circuit, a phase comparator 31, a selector 76, a loop filter 2, and a VCSO/VCXO 4 form a PLL circuit's main feedback loop during normal operation. When the main feedback loop of the PLL circuit malfunctions due to unlocking, a quartz crystal oscillator circuit is used, and a PLL circuit's backup feedback loop is established, which includes a backup phase comparator 74, the selector 76, the loop filter 2, and the VCSO/VCXO 4.

Abstract: A semiconductor device has a DLL circuit for generating an internal clock signal by receiving an external clock signal, wherein the DLL circuit includes a delay model for modeling delay time of an intern clock signal delayed from an external clock signal and a power supply for adjusting a core voltage by an input output voltage and supplying the adjusted voltage to the delay model.

Abstract: A generating a digital wave apparatus is provided. The period of a basic clock signal is divided into a plurality of time points, and the level of the highly accurate digital wave is toggled at these time points. The apparatus comprises a delay phase lock loop, for generating a plurality of delayed clock signals according to the basic clock signal; a first multiplexer and a second multiplexer for outputting one of the delayed clock signals according to a first select signal and a second select signal, respectively; a first edge-triggered flip-flop and a second edge-triggered flip-flop for receiving the output signals of the first multiplexer and the second multiplexer respectively; and a logic gate for outputting the digital wave according to the outputs of the first and the second edge-triggered flip-flops. The digital wave is toggled according to the first select signal, and further toggled according to the second select signal.

Abstract: A variable gain amplifier device comprises a variable gain amplifier circuit which amplifies a difference between an input signal and a feedback signal to output an output signal, a feedback circuit which supplies the feedback signal to the variable gain amplifier circuit, and a controller which controls the variable gain amplifier circuit and the feedback circuit to decrease a cutoff frequency of the feedback circuit according to increase of a gain of the variable gain amplifier circuit or vice versa.