Abstract: A digital system comprises a digital data processing unit, at least one output buffer connected to the processing unit to generate output signals in response to digital signals arriving from the processing unit and at least one user unit connect as output buffer load. With a view to assuring that the switching current of the output buffer can be set to different values, the output buffer comprises means for fixing the switching current to a value that is substantially constant and independent of the load and means for selectively setting the value of the switching current and the processing unit comprises means for storing a predetermined parameter; said means are connected to the selective setting means for setting the values of the switching current as functions of the predetermined parameter.

Abstract: A method and device program a dual edge programmable delay unit, that responds to an input signal with a rise time and a fall time, includes a buffer which receives the input signal and provides an output signal with programmed variable delays between the rise and fall times of the output signal. Programmable control sources (PCS) provide separate control inputs to a buffer. The FTPCS charges a capacitor in the buffer when the input signal changes from high to low to adjust time delay before the fall of the buffer output signal. The RTPCS discharges the capacitor in the buffer when the input signal changes from low to high to adjust time delay before the rise of the buffer output signal.

Abstract: A method and structure for providing dynamic control of a slew rate of an electronic circuit. The structure has a signal line that is coupled to a number of capacitive elements that may be selectively switched in or out of the electronic circuit in order to provide precise control of the slew rate of the electronic circuit. A control element switches the capacitive elements into the signal line so that the slew rate may be precisely controlled at one or more time instants. The method includes determining a desired slew rate of the electronic circuit. Based upon the desired value of the slew rate, one or more of the capacitive elements are switched into the signal line at one or more time instants without changing an output impedance of the electronic circuit.

Abstract: A transition delay matching circuit in which the transition delay of the divided clock signal is substantially the same as the transition delay of the reference clock signal. The transition delay of the divided clock signal is adjusted by reducing the steady state amplitude of the divided clock signal. Apparatuses and methods for matching the transition delays of the divided clock signal and the reference clock signal are disclosed.

Abstract: A fuse sense circuit has a sense amplifier and a post amplifier (gain stage). The sense amplifier has a reference branch and one or more sense (or fuse) branches. The fuse sense circuit determines the state of the fuses using safe currents and provides much higher gain than prior art. The post amplifier is a scaled replica of the reference branch or one of the sense branches in that the devices in the post amplifier maintain the same ratio as similar devices in the reference branch, and components in the post amplifier each matches components in the reference branch. The sense amplifier output is interpreted by the post amplifier's matched gain stage and has a trip point that sufficiently tracks the reference voltage. The result is reduced process and voltage sensitivity, which allows lower differential fuse resistance to be accurately detected with a non-ideal sense amplifier. Multiple gain stages may be added to multiple sense branches for redundancy and single-ended sensing.

Abstract: A high sensitivity, three-dimensional gamma ray detection and imaging system is provided. The system uses the Compton double scatter technique with recoil electron tracking. The system preferably includes two detector subassemblies; a silicon microstrip hodoscope and a calorimeter. In this system the incoming photon Compton scatters in the hodoscope. The second scatter layer is the calorimeter where the scattered gamma ray is totally absorbed. The recoil electron in the hodoscope is tracked through several detector planes until it stops. The x and y position signals from the first two planes of the electron track determine the direction of the recoil electron while the energy loss from all planes determines the energy of the recoil electron.

Abstract: An input stage circuit for an LVDS circuit. The input stage has a folded cascode that receives input signals. The folded cascode has a first input circuit and a second input circuit. The first input circuit receives a first input signal from a connected circuit and the second input circuit receives a second signal from the connected circuit. A first current mirror receives signals from the first input circuit of said folded cascode. A second current mirror receives signals from the second input circuit. The first current mirror and the second current mirror are connected to a common output to merge signals from the first and second input circuits. A diode adjusts a voltage level of the signals to an output voltage.

Abstract: A frequency generator (10) includes a direct digital synthesizer (14) having an accumulator (18 or 28) for providing an interim output and a digital interpolator (16) for interpolating the interim output to provide an output signal with reduced electromagnetic interference. The digital interpolator can include at least one converter among a digital-to-phase converter (22) or a digital-to-time converter (32). The frequency generator can further include a digitally programmable spreading function (12) applied to an input of the direct digital synthesizer.

Abstract: A duty-cycle adjustable buffer and a method for operating such buffer can be applied to a clock tree circuit for providing an adjustable duty cycle. The duty-cycle adjustable buffer includes a first inverter and a second inverter connected with each other in series. Each of the first inverter and the second inverter includes a plurality of controlled current charging paths and a plurality of controlled current discharging paths, wherein at least one controlled current charging path and at least one controlled current discharging path of the first inverter and the second inverter are conducted. The timing of the rising edge and falling edge of a clock signal is dynamically adjusted so as to dynamically altering the duty cycle of the clock signal.

Abstract: A timing control circuit includes a synchronization circuit and a detection circuit. The synchronization circuit includes a main delay line configured to receive an input clock signal and delay the input clock signal by a time interval to generate an output clock signal and a control circuit configured to control the main delay line to vary the time interval to synchronize the input clock signal with a feedback clock signal generated from the output clock signal responsive to assertion of an enable signal. The detection circuit is configured to receive the input clock signal and the feedback clock signal, detect a phase alignment error between the input clock signal and the feedback clock signal, and assert the enable signal responsive to the phase alignment error exceeding a predetermined amount.

Abstract: A quadrature switching mixer is provided for mixing a received RF signal and a local oscillator signal, while rejecting an image signal associated with the RF signal. Input signal components in quadrature, that is, I and Q input components derived from the received RF signal, are respectively coupled through first and second input paths to corresponding commuting switches in a configuration of switches. Each of the switches operates to multiply respective quadrature components of RF and local oscillator signals to provide quadrature output signal components. A unidirectional device, such as a buffer amplifier included in a signal splitter, is placed in each input path to prevent any portion of an output signal component from leaking backward through one of the input paths to the other input path, and thus to the other output signal component.

Abstract: A method of adjusting a control signal that includes generating a control signal at an unknown frequency and automatically adjusting the unknown frequency of the control signal based on the unknown frequency.

Abstract: In a first aspect, a cross-coupled inverter is provided that includes a first inverter circuit having a first NFET coupled to a first PFET and a second inverter circuit having a second NFET coupled to a second PFET. The second inverter circuit is cross-coupled with the first inverter circuit at a plurality of nodes. The body of at least one of the first NFET, the second NFET, the first PFET and the second PFET is coupled so as to form a feedback path that reduces discharging at one or more of the plurality of nodes in response to a soft error event at the cross-coupled inverter.

Abstract: An apparatus and method for a controlled current source are provided. The apparatus may include at least one current cell. Each current cell includes first, second and third transistors. The first transistor can be configured as a switch transistor. The second transistor can be configured as a current controller and can be coupled in series with the first transistor. The third transistor has a gate and a substrate coupled to a gate and a substrate of the second transistor, respectively. The drain and source of the third transistor can be coupled to a second input configured to receive a second signal that is a compliment of a first signal received at an input of the first transistor.

Abstract: The present invention is directed to an oil burner system having an electric cord set coupled between a controller and a valve associated with a pump. The electric cord set is operable to activate a solenoid valve associated with the pump for delivery of fuel oil to a nozzle of the burner. The electric cord set comprises a voltage or temperature independent timer circuit operable to activate the solenoid valve a predetermined period of time after a call for ignition signal is generated by the controller, wherein the predetermined time period is substantially constant with respect to variations in line voltage or in an ambient temperature in which the oil burner system resides.

Abstract: An overvoltage circuit detects differences between the supply voltage from a first circuit and the operating voltage of a second circuit. The circuit may detect when the power supply value of the first circuit is below, above, or equal to the operating voltage of the second circuit. The overvoltage circuit consumes substantially zero static current and may be used in a variety of implementations.

Abstract: Embodiments of the present invention relate to a circuit that varies the delay time of a clock signal in response to a frequency of the clock signal. The circuit may include a sensor and a delay circuit. The sensor may output a determination of the frequency of the clock signal. The delay time of the delay circuit may be responsive to the determination of a frequency of the clock signal. Accordingly, when the frequency of a clock signal varies, a delay of that clock signal can be varied to accommodate for the change in frequency.

Abstract: An apparatus for comparing an input voltage with a threshold voltage includes: (a) a first current mirror device that includes a first bipolar transistor with a first base and a first collector; the first base and the first collector establish a diode-connected first collector; the input voltage is received at the first current mirror device; (b) a second current mirror device that includes a second bipolar transistor with a second base and a second collector; the second base and the second collector establish a diode-connected second collector; (c) a first impedance coupled in series with the diode-connected first collector and the diode-connected second collector; and (d) a second impedance coupled between ground and the second current mirror device. The first and second current mirror devices are coupled with an output locus at which output signals appear to indicate relative voltage levels of the input and the threshold voltages.

Abstract: A semiconductor integrated circuit device includes a differential output driver circuit arranged at each I/O portion, and a delay element. The differential output driver circuit receives a pair of differential signals generated by a circuit on the input stage. An output signal from the differential output driver circuit is transmitted through the first and second signal lines. Each of the first and second signal lines includes a global interconnection, bump, and transmission line. The delay element is inserted in at least one of the first and second signal lines. The delay element delays signals passing through the signal lines so as to make the delays of the signals substantially equal to each other, compensating for the signal delay time generated by the line length difference.

Abstract: An output clock-pulse with a variable pulse duty factor is generated from a basic clock pulse that is supplied to a pulse contractor for generating pulses that are synchronized to the clock pulse. The resulting pulses are supplied to a circuit for varying the pulse duty factor corresponding to a ratio between the high-level and low-level of a period of the output clock-pulse.