Patents Examined by N. Drew Richards
  • Patent number: 8692281
    Abstract: This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: April 8, 2014
    Assignee: DiCon Fiberoptics Inc.
    Inventors: Wen-Herng Su, Junying Lu, Ho-Shang Lee
  • Patent number: 8664116
    Abstract: Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: March 4, 2014
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventors: Kazuhiko Fuse, Shinichi Kato
  • Patent number: 8659126
    Abstract: The present disclosure provides an Integrated Circuit (IC) device. The IC device includes a first die that contains an electronic component. The IC device includes second die that contains a ground shielding structure. The IC device includes a layer disposed between the first die and the second die. The layer couples the first die and the second die together. The present disclosure also involves a microelectronic device. The microelectronic device includes a first die that contains a plurality of first interconnect layers. An inductor coil structure is disposed in a subset of the first interconnect layers. The microelectronic device includes a second die that contains a plurality of second interconnect layers. A patterned ground shielding (PGS) structure is disposed in a subset of the second interconnect layers. The microelectronic device includes an underfill layer disposed between the first and second dies. The underfill layer contains one or more microbumps.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: February 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ling Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chewn-Pu Jou
  • Patent number: 8653637
    Abstract: A semiconductor device includes a first semiconductor package having at least one first semiconductor chip and a first sealing member covering the at least one first semiconductor chip. The semiconductor device also includes a second semiconductor package stacked on the first semiconductor package. The second semiconductor package has at least one second semiconductor chip, leads electrically connected to the at least one second semiconductor chip, and a second sealing member covering the at least one second semiconductor chip. At least one signal connection member is disposed in the first sealing member of the first semiconductor package. The at least one signal connection member electrically connects the at least one first semiconductor chip with the leads of the at least one second semiconductor chip.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: February 18, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-man Kim, In-sang Song
  • Patent number: 8648365
    Abstract: Disclosed is a light emitting device package. The light emitting device package includes a package body including a cavity formed therein with first and second via holes, a first electrode extending from one side of the cavity to one side of a rear surface of the package body through the first via hole, a second electrode extending from an opposite side of the cavity to an opposite side of the rear surface of the package body through the second via hole, a light emitting device connected with the first and second electrodes, an insulating layer insulating the first and second electrodes from the package body, and a reflective layer disposed on the insulating layer having a structure in which first and second media having different refractive indexes are alternately stacked on each other.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: February 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Jung Min Won
  • Patent number: 8647935
    Abstract: A method patterns at least one pair of openings through a protective layer and into a substrate. The openings are positioned on opposite sides of a channel region of the substrate. The method forms sidewall spacers along the sidewalls of the openings and removes additional substrate material from the bottom of the openings. The material removal process creates an extended bottom within the openings. The method forms a first strain producing material within the extended bottom of the openings. The method removes the sidewall spacers and forms a second material within the remainder of the openings between the first strain producing material and the top of the openings. The method removes the protective layer and forms a gate dielectric and a gate conductor on the horizontal surface on the substrate adjacent the channel region. The second material comprises source and drain regions.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Andreas Scholze
  • Patent number: 8647929
    Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A preferred embodiment includes a semiconductor device comprising a workpiece, the workpiece including a first region and a second region proximate the first region. A first material is disposed in the first region, and at least one region of a second material is disposed within the first material in the first region, the second material comprising a different material than the first material. The at least one region of the second material increases a first stress of the first region.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: February 11, 2014
    Assignee: Infineon Technologies AG
    Inventor: Jin-Ping Han
  • Patent number: 8643031
    Abstract: There is provided a pixel structure of a liquid crystal panel including a transparent substrate, and a gate line, a data line, a switching transistor, a first electrode, a second electrode and a shield layer formed on the transparent substrate. The gate line is substantially perpendicular to the data line. The switching transistor is located adjacent to a crossing point of the gate line and the data line, and is configured to input a display voltage of the data line to the second electrode according to the control of the gate line. The first electrode and the second electrode are arranged in such a way that the display voltage forms a transverse electric field between the first electrode and the second electrode. The shield layer overlaps at least a part of the gate and is electrically isolated from the first electrode and the second electrode.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: February 4, 2014
    Assignee: HannStar Display Corp.
    Inventors: Chia Hua Yu, I Fang Wang, Feng Weei Kuo, Jui Chi Lai, Ko Ruey Jen, Guang Shiung Chao
  • Patent number: 8642441
    Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: February 4, 2014
    Assignee: Spansion LLC
    Inventors: Tim Thurgate, Shenqing Fang, Kuo-Tung Chang, YouSeok Suh, Meng Ding, Hidehiko Shiraiwa, Amol Joshi, Harpreet Sachar, David Matsumoto, Lovejeet Singh, Chih-Yuh Yang
  • Patent number: 8642474
    Abstract: Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from the upper surface of the first mask pattern and the first mask pattern to form a second mask pattern comprising remaining portions of the cross-linked spacer, and etching using the second mask pattern to form an ultrafine pattern in the underlying target layer.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: February 4, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ryoung-han Kim, Yunfei Deng, Thomas I. Wallow, Bruno La Fontaine
  • Patent number: 8637854
    Abstract: The present invention provides a stacked organic light emitting diode that comprises a first electrode; a second electrode; and at least two light emitting units that are located between the first electrode and the second electrode. The light emitting unit satisfies the following energy relation equation, and includes an n-type organic layer and a p-type organic layer that form NP conjunction, and also includes an n-type doped organic layer that is located between the light emitting units: EpH?EnL?1 eV wherein EnL is a LUMO (lowest unoccupied molecular orbital) energy level of the n-type organic layer and EpH is a HOMO (highest occupied molecular orbital) energy level of the p-type organic layer.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: January 28, 2014
    Assignee: LG Chem, Ltd.
    Inventors: Min-Soo Kang, Jeoung-Kwen Noh, Se-Hwan Son, Jung-Bum Kim
  • Patent number: 8637912
    Abstract: A semiconductor device includes a substrate having a primary side. A first pillar extends vertically with respect to the primary side of the substrate, the first pillar defining first and second conductive regions and a channel region that is provided between the first and second conductive regions. A first gate is provided over the channel region of the first pillar. A buried word line extends along a first direction below the first pillar, the buried word line configured to provide a first control signal to the first gate. A first interposer is coupled with the buried word line and the first gate to enable the first control signal to be applied to the first gate via the buried word line.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 28, 2014
    Assignee: SK Hynix Inc.
    Inventor: Jinchul Park
  • Patent number: 8637399
    Abstract: An etching composition for a copper-containing layer includes about 0.1% to about 30% by weight of ammonium persulfate, about 0.1% to about 10% by weight of a sulfate, about 0.01% to about 5% by weight of an acetate and about 55% to about 99.79% by weight of water. The etching composition having improved stability during storage and an increased capacity for etching.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: January 28, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hong-Sick Park, Bong-Kyun Kim, Wang-Woo Lee, Ki-Beom Lee, Sam-Young Cho, Won-Guk Seo, Gyu-Po Kim
  • Patent number: 8633118
    Abstract: Methods for forming thin metal and semi-metal layers by thermal remote oxygen scavenging are described. In one embodiment, the method includes forming an oxide layer containing a metal or a semi-metal on a substrate, where the semi-metal excludes silicon, forming a diffusion layer on the oxide layer, forming an oxygen scavenging layer on the diffusion layer, and performing an anneal that reduces the oxide layer to a corresponding metal or semi-metal layer by oxygen diffusion from the oxide layer to the oxygen scavenging layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 21, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Patent number: 8633037
    Abstract: A semiconductor device includes a substrate having a main surface and a rear surface, a transistor formed over a side of the main surface, an insulator layer formed over a side of the main surface, an inductor formed over the insulator layer and a side of the main surface, a tape overlapping the inductor and formed over a side of the main surface, and a bonding pad formed over the insulating layer and a side of the main surface. The tape is selectively formed over an area without the bonding pad.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: January 21, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Masayuki Furumiya, Yasutaka Nakashiba
  • Patent number: 8633113
    Abstract: A method for fabricating a bottom oxide layer in a trench (102) is disclosed. The method comprises forming the trench (102) in a semiconductor substrate (100), depositing an oxide layer to partially fill a field area (104) and the trench (102), wherein said oxide layer has oxide overhang portions (106) and removing the oxide overhang portions (106) of the deposited oxide layer. Thereafter, the method comprises forming a bottom anti-reflective coating (BARC) layer (108) to cover the oxide layer in the field area (104) and the trench (102), removing the BARC layer (110) from the field area (104), while retaining a predetermined thickness of the BARC layer (112) in the trench (102), removing the oxide layer from the field area (104) and removing the BARC layer and oxide layer in the trench (102) to obtain a predetermined thickness of the bottom oxide layer (114).
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: January 21, 2014
    Assignee: Silterra Malaysia Sdn Bhd
    Inventors: Charlie Tay, Venkatesh Madhaven, Arjun K. Kantimahanti
  • Patent number: 8633582
    Abstract: A chip package is disclosed. The package includes a carrier substrate and at least one semiconductor chip thereon. The semiconductor chip has a plurality of conductive pads, where a plurality of first redistribution layers (RDLs) is disposed thereon and is electrically connected thereto. A single-layer insulating structure covers the carrier substrate and the semiconductor chip, having a plurality of openings exposing the plurality of first RDLs. A plurality of second RDLs is disposed on the single-layer insulating structure and is electrically connected to the plurality of first RDLs. A passivation layer is disposed on the single-layer insulating structure and the plurality of second RDLs, having a plurality of openings exposing the plurality of second RDLs. A plurality of conductive bumps is correspondingly disposed in the plurality of openings to be electrically connected to the plurality of second RDLs. A fabrication method of the chip package is also disclosed.
    Type: Grant
    Filed: February 9, 2010
    Date of Patent: January 21, 2014
    Inventors: Shu-Ming Chang, Cheng-Te Chou
  • Patent number: 8614515
    Abstract: A wiring method for a semiconductor integrated circuit has the steps of, separately from a first layer on which a first signal wiring pattern is mainly formed, laying out a first power-supply wiring pattern on a second layer so that a plurality of rows of the first power-supply wiring pattern are regularly arranged with vacant areas each interposed between the rows and making narrower a width of each vacant area than a narrowest width of a row among the rows of the first power-supply wiring pattern, and laying out a second signal wiring pattern electrically conductive to the first layer in two or more rows of the vacant areas on the second layer so that the second signal wiring pattern is not in contact with adjacent rows of the first power-supply wiring pattern on both sides.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 24, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuaki Utsumi
  • Patent number: 8610243
    Abstract: Disclosed herein is a metal e-fuse device that employs an intermetallic compound programming mechanism and various methods of making such an e-fuse device. In one example, a device disclosed herein includes a first metal line, a second metal line and a fuse element that is positioned between and conductively coupled to each of the first and second metal lines, wherein the fuse element is adapted to be blown by passing a programming current therethrough, and wherein the fuse element is comprised of a material that is different from a material of construction of at least one of the first and second metal lines.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: December 17, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jens Poppe, Andreas Kurz
  • Patent number: 8609489
    Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: David A. Kewley, Brian Cleereman, Stephen W. Russell, Rex Stone, Anthony C. Krauth