Abstract: A memory device of a resistance variation type, in which data retaining characteristic at the time of writing is improved, is provided. The memory device includes: a plurality of memory elements in which a memory layer is provided between a first electrode and a second electrode so that data is written or erased in accordance with a variation in electrical characteristics of the memory layer; and pulse applying means applying a voltage pulse or a current pulse selectively to the plurality of memory elements. The memory layer includes an ion source layer including an ionic-conduction material and at least one kind of metallic element, and the ion source layer further contains oxygen.

Abstract: A semiconductor structure and a method for fabricating the semiconductor structure include a hybrid orientation substrate having a first active region having a first crystallographic orientation that is vertically separated from a second active region having a second crystallographic orientation different than the first crystallographic orientation. A first field effect device having a first gate electrode is located and formed within and upon the first active region and a second field effect device having a second gate electrode is located and formed within and upon the second active region. Upper surfaces of the first gate electrode and the second gate electrode are coplanar. The structure and method allow for avoidance of epitaxial defects generally encountered when using hybrid orientation technology substrates that include coplanar active regions.

Abstract: A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

Abstract: In a liquid crystal display device that uses a top gate TFT, a contact hole is formed to connect to an image signal line. An inorganic passivation film and an organic passivation film are formed in this order so as to cover the TFT, on which a common electrode is formed. Then, an interlayer insulating film is formed on the common electrode. A through hole for gas release is formed in the interlayer insulating film. The diameter of the through hole is greater than the diameter of the contact hole, so as to be able to easily release gas from the organic passivation film, and to prevent the interlayer insulating film from peeling off.

Abstract: A method of manufacturing a laser diode device includes: forming, in a semiconductor laser bar, separation trenches extending across all of a transverse dimension of the semiconductor laser bar and defining a mesa stripe, each of the separation trenches having wide portions located at longitudinal edge portions of the semiconductor laser bar and a narrow portion located in a longitudinal central portion of the semiconductor laser bar; scribing, in the semiconductor laser bar, grooves extending parallel to the separation trenches and terminating before reaching longitudinal edge portions of the semiconductor laser bar; and splitting the semiconductor laser bar along the grooves to form cleaved surfaces extending from a bottom surface of the semiconductor laser bar to bottom surfaces of the separation trenches.

Abstract: A micromechanical systems (MEMs) pressure sensor includes a semiconductor substrate having a deep well located within a first surface and a cavity located within a second, opposing surface. The semiconductor substrate has a first doping type. The deep well has a second doping type, with a gradient doping profile, thereby forming a PN junction within the substrate. The cavity forms a diaphragm, which is a substrate section that is thinner than the surrounding substrate sections, that comprises the deep well. One or more pizeoresistor elements are located within the deep well. The piezoresistors are sensitive to deformations, such as bending, in the diaphragm caused by changes in the pressure of the cavity.

Abstract: Wafer level packaging (WLP) packages semiconductor dies onto a wafer structure. After the wafer level package is complete, individual packages are obtained by singulating the wafer level package. The resulting package has a small form factor suitable for miniaturization. Unfortunately conventional WLP have poor heat dissipation. An interposer with a thermal pad can be attached to the semiconductor die to facilitate improved heat dissipation. In one embodiment, the interposer can also provide a wafer substrate for the wafer level package. Furthermore, the interposer can be constructed using well established and inexpensive processes. The thermal pad attached to the interposer can be coupled to the ground plane of a system where heat drawn from the semiconductor die can be dissipated.

Abstract: Provided are power device packages, which include thermal electric modules using the Peltier effect and thus can improve operational reliability by rapidly dissipating heat generated during operation to the outside, and methods of fabricating the same. An exemplary power device package includes: a thermal electric module having a first surface and a second surface opposite each other, and a plurality of n-type impurity elements and a plurality of p-type impurity elements alternately and electrically connected to each other in series; a lead frame attached to the first surface of the thermal electric module by an adhesive member; at least one power semiconductor chip and at least one control semiconductor chip, each chip being mounted on and electrically connected to the lead frame; and a sealing member sealing the thermal electric module, the chips, and at least a portion of the lead frame, but exposing the second surface of the module.

Abstract: A method of making a LED includes following steps. A substrate with an epitaxial growth surface is provided. A carbon nanotube layer is placed on the epitaxial growth surface. A semiconductor epitaxial layer is grown on the epitaxial growth surface, and the semiconductor epitaxial layer includes an N-type semiconductor layer, an active layer, a P-type semiconductor layer. The semiconductor epitaxial layer is etched to expose part of the carbon nanotube layer. A first electrode is formed on a surface of the semiconductor epitaxial layer which is away from the substrate. A second electrode is formed to electrically connect with the part of the carbon nanotube layer which is exposed.

Abstract: A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance.

Abstract: According to one embodiment, an opening pattern is formed in the core film above a processing target, and a mask film is conformably formed above the processing target. Next, etch-back of the mask film is performed so that the mask film remains on a side surface of the core film. After that, line-and-space shaped core patterns, made of the core film, is formed in an area other than an area forming the opening pattern. Next, sidewall patterns are formed around the core patterns, and the core patterns are removed. Next, the processing target is patterned by using the mask film and the sidewall patterns.

Abstract: An LED package includes an electrode, an LED chip, and an insulation layer. The electrode includes a first electrode and a second electrode. The first electrode and the second electrode are separate from each other. The LED chips are connected to the first and second electrodes. The insulation layer covers the first and second electrodes and the LED chip. A cavity is defined in the first electrode for receiving the LED chip therein. A channel is defined between the first electrode and the second electrode. The channel communicates with the cavity and the insulation layer fills in the cavity and the channel.

Abstract: The present invention is to provide a semiconductor device in which the step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed. A semiconductor device of the present invention includes an antenna, a storage element, and a transistor, wherein a conductive layer serving as an antenna is provided in the same layer as a conductive layer of the transistor or the storage element. This characteristic makes it possible to omit an independent step of forming the conductive layer serving as an antenna and to conduct the step of forming the conductive layer serving as an antenna at the same time as the step of forming a conductive layer of another element. Therefore, the manufacturing step can be simplified, the manufacturing cost can be suppressed, and the decrease in yield can be suppressed.

Abstract: To provide an integrated circuit with functionality under environment with temperature lower than a working condition, the integrated circuit is designed to include a heating element incorporated with signal pins on a carrier, such as a lead frame, that supports a chip die and controlled by a heating control unit to increase temperature of the chip die. The heating control unit provides voltage for the heating element when a detecting unit detects that the temperature of the chip die falls below a predetermined temperature and a power control unit provide operation power for the chip die when the temperature of the chip die detected by the detecting unit reaches or falls above the predetermined temperature.

Abstract: It is an object of the present invention to provide a method of separating a thin film transistor, and circuit or a semiconductor device including the thin film transistor from a substrate by a method different from that disclosed in the patent document 1 and transposing the thin film transistor, and the circuit or the semiconductor device to a substrate having flexibility. According to the present invention, a large opening or a plurality of openings is formed at an insulating film, a conductive film connected to a thin film transistor is formed at the opening, and a peeling layer is removed, then, a layer having the thin film transistor is transposed to a substrate provided with a conductive film or the like. A thin film transistor according to the present invention has a semiconductor film which is crystallized by laser irradiation and prevents a peeling layer from exposing at laser irradiation not to be irradiated with laser light.

Abstract: Superjunction collectors for transistors are discussed in this application. According to one embodiment, a bipolar transistor having a superjunction collector structure can comprise a collector electrode, a base electrode, an emitter electrode, a collector-base space charge region, and a superjunction collector. The collector-base space charge region can be disposed in electrical communication between the collector electrode and the base electrode. The superjunction collector region can be disposed in the collector-base space charge region. The superjunction collector region can comprise a plurality of alternating horizontally disposed P-type and N-type layers. The layers can be horizontally disposed layers that are layered on top of each other. The P-type and N-type layers can be doped with different types of doping levels. Other aspects, embodiments, and features are also discussed and claimed.

Abstract: It is an object to provide a technique to improve electric characteristics after a high-temperature treatment even when a high melting point metal barrier layer is not formed. A semiconductor device includes a gate electrode formed on a transparent insulation substrate, a semiconductor layer having a Si semiconductor active film and an ohmic low resistance Si film having an n-type conductivity, being formed in this order on the gate electrode with a gate insulation film interposed between the gate electrode and the semiconductor layer, and the source and drain electrodes directly connected to the semiconductor layer and containing at least aluminum (Al). At least nitrogen (N) is contained in a first region that is in the vicinity of an interface between a side surface of the SI semiconductor active film and the source and drain electrodes.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a control electrode, a first main electrode, an internal electrode, and an insulating region. The control electrode is provided inside a trench. The first main electrode is in conduction with the third semiconductor region. The internal electrode is provided in the trench and in conduction with the first main electrode. The insulating region is provided between an inner wall of the trench and the internal electrode. The internal electrode includes a first internal electrode part included in a first region of the trench and a second internal electrode part included in a second region between the first region and the first main electrode. A spacing between the first internal electrode part and the inner wall is wider than a spacing between the second internal electrode part and the inner wall.

Abstract: The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.

Abstract: A thyristor device includes a semiconductor body and a conductive anode. The semiconductor body has a plurality of doped layers forming a plurality of dopant junctions and includes an optical thyristor, a first amplifying thyristor, and a switching thyristor. The conductive anode is disposed on a first side of the semiconductor body. The optical thyristor is configured to receive incident radiation to generate a first electric current, and the first amplifying thyristor is configured to increase the first electric current from the optical thyristor to at least a threshold current. The switching thyristor switches to the conducting state in order to conduct a second electric current from the anode and through the semiconductor body.