Abstract: A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.

Abstract: A device including a semiconductor on insulator (SOI) substrate including a semiconductor device region and a capacitor device region. A semiconductor device present in the semiconductor device region. The semiconductor device including a gate structure present on a semiconductor on insulator (SOI) layer of the SOI substrate, extension source and drain regions present in the SOI layer on opposing sides of the gate structure, and raised source and drain regions composed of a first portion of an epitaxial semiconductor material on the SOI layer. A capacitor is present in the capacitor device region, said capacitor including a first electrode comprised of a second portion of the epitaxial semiconductor material that has a same composition and crystal structure as the first portion of the epitaxial semiconductor material, a node dielectric layer present on the second portion of the epitaxial semiconductor material, and a second electrode comprised of a conductive material.

Abstract: A method for fabricating a recessed channel access transistor device is provided. A semiconductor substrate having thereon a recess is provided. A gate dielectric layer is formed in the recess. A gate material layer is then deposited into the recess. A dielectric cap layer is formed on the gate material layer. The dielectric cap layer and the gate material layer are etched to form a gate pattern. A liner layer is then formed on the gate pattern. A spacer is formed on the liner layer on each sidewall of the gate pattern. The liner layer not masked by the spacer is etched to form an undercut recess that exposes a portion of the gate material layer. The spacer is then removed. The exposed portion of the gate material layer in the undercut recess is oxidized to form an insulation block therein.

Abstract: Systems, methods and devices for the efficient photocurrent generation in single- or multi-walled carbon nanotubes, which includes (SWNTs)/poly [3-hexylthiophene-2,5-diyl] (P3HT) hybrid photovoltaics, and exhibit the following features: photocurrent measurement at individual SWNT/P3HT heterojunctions indicate that both semiconducting (s-) and metallic (m-) SWNTs function as excellent hole acceptors; electrical transport and gate voltage dependent photocurrent indicate that P3HT p-dopes both s-SWNT and m-SWNT, and exciton dissociation is driven by a built-in voltage at the heterojunction. Some embodiments include a mm2 scale SWNT/P3HT bilayer hybrid photovoltaics using horizontally aligned SWNT arrays, which exhibit greater than 90% effective external quantum efficiency, among other things, which advantageously provide carbon nanomaterial based low cost and high efficiency hybrid photovoltaics.

Abstract: An amorphous oxide semiconductor contains at least one element selected from In, Ga, and Zn at an atomic ratio of InxGayZnz, wherein the density M of the amorphous oxide semiconductor is represented by the relational expression (1) below: M?0.94×(7.121x+5.941y+5.675z)/(x+y+z)??(1) where 0?x?1, 0?y?1, 0?z?1, and x+y+z?0.

Abstract: The present invention discloses a double gate transistor and a method of fabricating said transistor, said transistor comprising: a semiconductor layer on a substrate; a fin structure formed in said semiconductor layer, said fin structure having two end portions for forming source and drain regions and a middle portion between said two end portions for forming a channel region, said middle portion including two opposed side surfaces perpendicular to a substrate surface; a first gate dielectric layer and a first gate disposed on one side surface of said middle portion; and a second gate dielectric layer and a second gate disposed on the other side surface of said middle portion.

Abstract: A semiconductor substrate which allows desired electrical characteristics to be more easily acquired, a semiconductor device of the same, and a method of producing the semiconductor substrate. The method of producing this semiconductor substrate is provided with: a first epitaxial layer forming step (S1) of forming a first epitaxial layer; a trench forming step (S2) of forming trenches in the first epitaxial layer; and epitaxial layer forming steps (S3, S4, S5) of forming epitaxial layers on the first epitaxial layer and inside the trenches, using a plurality of growth conditions including differing growth rates, so as to fill the trenches, and keeping the concentration of dopant taken into the epitaxial layers constant in the plurality of growth conditions.

Abstract: A light emitting device package includes a body, a first reflective cup and a second reflective cup disposed in a top surface of the body spaced from each other, a connection pad disposed in the top surface of the body spaced apart from the first reflective cup and the second reflective cup, a recess formed in the top surface of the body spaced apart from the first reflective cup, the second reflective cup, and the connection pad, a first semiconductor light emitting device disposed in the first reflective cup, a second semiconductor light emitting device disposed in the second reflective cup, and a Zener diode disposed in the recess, wherein the first reflective cup and the second reflective cup are recessed from the top surface of the body.

Abstract: To realize miniaturization/high integration and increase in the amount of accumulated charges, and to give a memory structure having a high reliability. A 1 transistor 1 capacitor (1T1C) structure having 1 ferroelectric capacitor structure and 1 selection transistor every memory cell is adopted, and respective capacitor structures are disposed respectively in either one layer of interlayer insulating films of 2 layers having different heights from the surface of a semiconductor substrate.

Abstract: A semiconductor device includes a semiconductor substrate including a cell area and a peripheral circuit area, a first trench for device isolation formed in the cell area of the semiconductor substrate and a second trench for device isolation formed within the semiconductor substrate of the peripheral circuit area to be deeper than the first trench, a device isolation layer buried within the first and second trenches for device isolation and having the same surface level as the semiconductor substrate in the cell area, a buried gate buried in the semiconductor substrate of the cell area, and a peripheral circuit gate which is in contact with the semiconductor substrate of the peripheral circuit area, is buried within the device isolation layer of the peripheral circuit area, and has the same surface level as the buried gate.

Abstract: An LED includes a base, a pair of leads fixed on the base, a housing fixed on the leads, a chip mounted on one lead and an encapsulant sealing the chip. The housing defines a cavity in a central area thereof and a chamber adjacent to a circumferential periphery thereof. Top faces of the leads are exposed in the chamber. A blocking wall is formed in the chamber to contact the exposed top faces of the leads. A bonding force between the blocking wall and the leads is larger than that between the leads and the housing. A method for manufacturing the LED is also disclosed.

Abstract: A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.

Abstract: A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.

Abstract: According to one embodiment, there is provided a semiconductor device including a semiconductor substrate, an edge seal, a plurality of pad pieces, and an insulating film pattern. The semiconductor substrate includes a chip area formed at an inward side of the semiconductor substrate when viewed in a direction perpendicular to a surface of the semiconductor substrate. The edge seal is disposed around the chip area on the surface to protect the chip area. The plurality of pad pieces are disposed on an edge region on the surface. The insulating film pattern covers edge portions of the plurality of pad pieces at a side of the edge seal, at least at one side of the chip area on the surface in a first direction and at least at one side of the chip area on the surface in a second direction.

Abstract: A semiconductor package and related methods are described. In one embodiment, the package includes a die pad, a plurality of leads, a chip, and a package body. The die pad includes: (1) a peripheral edge region defining, a cavity with a cavity bottom including a central portion; (2) an upper sloped portion; and (3) a lower sloped portion. Each lead includes an upper sloped portion and a lower sloped portion. The chip is disposed on the central portion of the cavity bottom and is coupled to the leads. The package body is formed over the chip and the leads, substantially fills the cavity, and substantially covers the upper sloped portions of the die pad and the leads. The lower sloped portions of the die pad and the leads at least partially extend outwardly from a lower surface of the package body.

Abstract: A thin film transistor (TFT) substrate and a manufacturing method thereof are disclosed. The manufacturing method comprises: after a first metallic layer is formed on the TFT substrate, annealing the TFT substrate so that lattices of the first metallic layer are re-arranged to prevent occurrences of grain boundary defects in the first metallic layer. According to the present disclosure, after the first metallic layer is formed on the TFT substrate, the TFT substrate is annealed in sequence to re-arrange lattices of the first metallic layer. This effectively prevents occurrences of grain boundary defects and, consequently, metal protrusions in the first metallic layer.

Abstract: A thin-film transistor array device includes a passivation film above first and second bottom gate transistors. A gate wire is below the passivation film. A source wire and a relay wire are above the passivation film. The source wire is electrically connected to a source electrode of the first transistor via a first hole in the passivation film. A conductive oxide film is between the passivation film and both the source wire and the relay electrode and not electrically connected between the source wire and the relay electrode. The conductive oxide film covers an end portion of the gate wire that is exposed via a second hole in the passivation film. The conductive oxide film is between the relay electrode and a current-supply electrode of the second transistor and electrically connects the relay electrode and the current-supply electrode via a third hole in the passivation film.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, forming a material layer over the substrate and the gate structure, implanting Ge, C, P, F, or B in the material layer, removing portions of the material layer overlying the substrate at either side of the gate structure, forming recesses in the substrate at either side of the gate structure, and depositing a semiconductor material in the recesses by an expitaxy process.

Abstract: A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.

Abstract: A high voltage semiconductor device is provided. A first-polarity buried layer is formed in the substrate. A first high voltage second-polarity well region is located over the first-polarity buried layer. A second-polarity base region is disposed within the first high voltage second-polarity well region. A source region is disposed within the second-polarity base region. A high voltage deep first-polarity well region is located over the first-polarity buried layer and closely around the first high voltage second-polarity well region. A first-polarity drift region is disposed within the high voltage deep first-polarity well region. A gate structure is disposed over the substrate. A second high voltage second-polarity well region is located over the first-polarity buried layer and closely around the high voltage deep first-polarity well region. A deep first-polarity well region is located over the first-polarity buried layer and closely around the second high voltage second-polarity well region.