Abstract: A bi-directional protection device includes a bi-directional NPN bipolar transistor including an emitter/collector formed from a first n-well region, a base formed from a p-well region, and a collector/emitter formed from a second n-well region. P-type active regions are formed in the first and second n-well regions to form a PNPNP structure, which is isolated from the substrate using dual-tub isolation consisting of an n-type tub and a p-type tub. The dual-tub isolation prevents induced latch-up during integrated circuit powered stress conditions by preventing the wells associated with the PNPNP structure from injecting carriers into the substrate. The size, spacing, and doping concentrations of active regions and wells associated with the PNPNP structure are selected to provide fine-tuned control of the trigger and holding voltage characteristics to enable the bi-directional protection device to be implemented in high voltage applications using low voltage precision interface signaling.

Abstract: Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures and across metal oxide. In some embodiments, the constructions may have a planarized surface extending across the platinum-containing structures, across a first material retaining the platinum-containing structures, and across metal oxide liners along sidewalls of the platinum-containing structures and directly between the platinum-containing structures and the first material. Some embodiments include methods of forming platinum-containing structures. In some embodiments, first material is formed across electrically conductive structures, and metal oxide is formed across the first material. Openings are formed to extend through the metal oxide and the first material to the electrically conductive structures. Platinum-containing material is formed within the openings and over the metal oxide.

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract: Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.

Abstract: A transistor power switch device comprising a semiconductor body presenting opposite first and second faces, an array of vertical field-effect transistor elements for carrying current between the first and second faces is provided. The array of transistor elements comprises at the first face an array of source regions of a first semiconductor type, at least one body region of a second semiconductor type opposite to the first type interposed between the source regions and the second face, at least one control electrode for switchably controlling flow of the current through the second transistor region, and a conductive layer contacting the source regions and insulated from the control electrode by at least one insulating layer.

Abstract: A bidirectional protection component formed in a semiconductor substrate of a first conductivity type including a first implanted area of the first conductivity type, an epitaxial layer of the second conductivity type on the substrate and the first implanted area, a second area of the first conductivity type on the external side of the epitaxial layer, in front of the first area, and implanted with the same dose as the first area, a first metallization covering the entire lower surface of the substrate, and a second metallization covering the second area.

Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

Abstract: A semiconductor device and its manufacturing method are offered to increase the number of semiconductor devices obtained from a semiconductor wafer while simplifying a manufacturing process. After forming a plurality of pad electrodes in a predetermined region on a top surface of a semiconductor substrate, a supporter is bonded to the top surface of the semiconductor substrate through an adhesive layer. Next, an opening is formed in the semiconductor substrate in a region overlapping the predetermined region. A wiring layer electrically connected with each of the pad electrodes is formed in the opening. After that, a stacked layer structure including the semiconductor substrate and the supporter is cut by dicing along a dicing line that is outside the opening.

Abstract: An electronic device can include a semiconductor layer, and a trench extending into the semiconductor layer and having a tapered shape. In an embodiment, the trench includes a wider portion and a narrower portion. The electronic device can include a doped semiconductor region that extends to a narrower portion of the trench and has a dopant concentration greater than a dopant concentration of the semiconductor layer. In another embodiment, the electronic device can include a conductive structure within a relatively narrower portion of the trench, and a conductive electrode within a relatively wider portion of the trench. In another embodiment, a process of forming the electronic device can include forming a sacrificial plug and may allow insulating layers of different thicknesses to be formed within the trench.

Abstract: In a power MISFET having a trench gate structure with a dummy gate electrode, a technique is provided for improving the performance of the power MISFET, while preventing electrostatic breakdown of a gate insulating film therein. A power MISFET having a trench gate structure with a dummy gate electrode, and a protective diode are formed on the same semiconductor substrate. The protective diode is provided between a source electrode and a gate interconnection. In a manufacturing method of such a semiconductor device, a polycrystalline silicon film for the dummy gate electrode and a polycrystalline silicon film for the protective diode are formed simultaneously. A source region of the power MISFET and an n+-type semiconductor region of the protective diode are formed in the same step.

Abstract: A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.

Abstract: It is an object of the present invention to provide a technique to manufacture a highly reliable display device at a low cost with high yield. A display device according to the present invention includes a semiconductor layer including an impurity region of one conductivity type; a gate insulating layer, a gate electrode layer, and a wiring layer in contact with the impurity region of one conductivity type, which are provided over the semiconductor layer; a conductive layer which is formed over the gate insulating layer and in contact with the wiring layer; a first electrode layer in contact with the conductive layer; an electroluminescent layer provided over the first electrode layer; and a second electrode layer, where the wiring layer is electrically connected to the first electrode layer with the conductive layer interposed therebetween.

Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.

Abstract: A method for fabricating high efficiency CIGS solar cells including the deposition of Ga concentrations (Ga/(Ga+In)=0.25?0.66) from sputtering targets containing Ga concentrations between about 25 atomic % and about 66 atomic %. Further, the method includes a high temperature selenization process integrated with a high temperature anneal process that results in high efficiency.

Abstract: One or more embodiments may include a method of making a semiconductor structure, comprising: forming a first opening partially through a semiconductor substrate; forming a first dielectric layer over a sidewall surface of the first opening; and forming a second opening partially through a semiconductor substrate, the second opening being below the first opening.

Abstract: Disclosed is a ferromagnetic tunnel junction structure which is characterized by having a tunnel barrier layer that comprises a non-magnetic material having a spinel structure. The ferromagnetic tunnel junction structure is also characterized in that the non-magnetic material is substantially MgAl2O4. The ferromagnetic tunnel junction is also characterized in that at least one of the ferromagnetic layers comprises a Co-based full Heusler alloy having an L21 or B2 structure. The ferromagnetic tunnel junction structure is also characterized in that the Co-based full Heusler alloy comprises a substance represented by the following formula: Co2FeAlxSi1-x (0?x?1). Also disclosed are a magnetoresistive element and a spintronics device, each of which utilizes the ferromagnetic tunnel junction structure and can achieve a high TMR value, that cannot be achieved by employing conventional tunnel barrier layers other than a MgO barrier.

Abstract: This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e.g., combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e.g.

Abstract: A method of fabricating a semiconductor device includes the following steps. At first, a semiconductor substrate is provided. A gate stack layer is formed on the semiconductor substrate, and the gate stack layer further includes a cap layer disposed thereon. Furthermore, two first spacers surrounding sidewalls of the gate stack layer is further formed. Subsequently, the cap layer is removed, and two second spacers are formed on a part of the gate stack layer. Afterwards, a part of the first spacers and the gate stack layer not overlapped with the two second spacers are removed to form two gate stack structures.

Abstract: An Enhancement-mode (E-mode) high electron mobility transistor (HEMT) includes a channel layer with a 2-Dimensional Electron Gas (2DEG), a barrier layer inducing the 2DEG in the channel layer, source and drain electrodes on the barrier layer, a depletion layer on the barrier layer between the source and drain electrodes, and a gate electrode on the depletion layer. The barrier layer is recessed below the gate electrode and the depletion layer covers a surface of the recess and extends onto the barrier layer around the recess.

Abstract: A semiconductor device such as a diode or transistor includes a semiconductor substrate, a first region of III-V semiconductor material on the semiconductor substrate and a second region of III-V semiconductor material on the first region. The second region is spaced apart from the semiconductor substrate by the first region. The second region is of a different composition than the first region. The semiconductor device further includes a buried contact extending from the semiconductor substrate to the second region through the first region. The buried contact electrically connects the second region to the semiconductor substrate.