Patents Examined by Natalia A Gondarenko
  • Patent number: 10978616
    Abstract: [Object] To provide a micro LED element that can reduce deterioration in light emission efficiency, even when the micro LED element is miniaturized in size. [Solution] A micro LED element (100) includes: a nitride semiconductor layer (14) including an N-side layer (11), a light emission layer (12), and a P-side layer (13); and a plurality of micro-mesas each having a slope that surrounds the light emission layer (12) and is inclined at an angle within a prescribed range including 45° as an angle (?) formed by the slope and the light emission layer, and a flat portion formed by a surface of the P-side layer.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: April 13, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Katsuji Iguchi
  • Patent number: 10978484
    Abstract: In some embodiments, a method used in forming an array of memory cells comprises uses no more than two photolithographic masking steps are used in forming both: (a) sense lines longitudinally extending in a column direction that are individually directly above and electrically coupled to the upper source/drain regions of multiple of the second pedestals in the column direction; and (b) spaced elevationally-extending vias laterally between immediately-adjacent of the sense lines directly above and electrically coupled to the upper source/drain regions of multiple of the first pedestals. Other embodiments are disclosed.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10978435
    Abstract: The present invention relates to a display device using a semiconductor light-emitting element and, particularly, to a display device using a semiconductor light-emitting element. A display device according to the present invention comprises: a substrate including a driving thin-film transistor; a semiconductor light-emitting element including a first conductive electrode and a second conductive electrode; and a planarization layer formed to cover the driving thin-film transistor and including a reception hole in which the semiconductor light-emitting element is received, wherein a height adjustment layer is formed between the substrate and the planarization layer so as to make one of the first and the second conductive electrode and one surface of the planarization layer coincide with each other in height.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 13, 2021
    Assignee: LG ELECTRONICS INC.
    Inventor: Seonhoo Kim
  • Patent number: 10971486
    Abstract: A semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee-Won Kang, Jong-Joo Lee
  • Patent number: 10964864
    Abstract: A light emitting structure including mixing cups are described. In an embodiment, a light emitting structure includes a light emitting diode (LED) bonded to a substrate, a diffuser layer adjacent the LED, an angular filter directly over the diffuser layer and the LED, and an overcoat layer directly over the angular filter and the LED.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 30, 2021
    Inventors: James Michael Perkins, Sergei Y. Yakovenko, Dmitry S. Sizov
  • Patent number: 10957600
    Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: March 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ryan Chia-Jen Chen, Yih-Ann Lin, Chia Tai Lin, Chao-Cheng Chen
  • Patent number: 10957825
    Abstract: A lighting module according to an embodiment of the invention includes: a substrate; a plurality of light emitting devices disposed in N rows (N is an integer of 1 or more) on the substrate; a first resin layer covering the plurality of light emitting devices; a first diffusion layer disposed on the first resin layer and diffusing light emitted from the first resin layer; and a second diffusion layer disposed on the first diffusion layer and diffusing light emitted from the first diffusion layer, wherein the first diffusion layer includes a diffusing agent, and the second diffusion layer includes at least one of a phosphor and ink particles.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: March 23, 2021
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sa Rum Han, Dong Il Eom, Young Hun Ryu
  • Patent number: 10950764
    Abstract: A light-emitting device includes: a first light-emitting element and a second light-emitting element, each having a peak emission wavelength in a range of 430 nm to 480 nm; and a sealing member covering the first light-emitting element and the second light-emitting element, the sealing member containing a first fluorescent material. The first light-emitting element and the second light-emitting element are configured to be individually driven. The sealing member includes a protruding portion at an upper surface thereof. The first light-emitting element is disposed in a first region, which is located under the protruding portion. The second light-emitting element is disposed in a second region, which is located under the upper surface of the sealing member at a position different from the first region.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 16, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Atsushi Bando, Kazuya Matsuda
  • Patent number: 10942408
    Abstract: A novel composite oxide semiconductor which can be used in a transistor including an oxide semiconductor film is provided. In the composite oxide semiconductor, a first region and a second region are mixed. The first region includes a plurality of first clusters containing In and oxygen as main components. The second region includes a plurality of second clusters containing Zn and oxygen as main components. The plurality of first clusters have portions connected to each other. The plurality of second clusters have portions connected to each other.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: March 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10943938
    Abstract: An image sensor including a substrate and an image sensing element is provided. The substrate has an arc surface. The image sensing element is disposed on the arc surface and curved to fit a contour of the arc surface. The image sensing element has a front surface and a rear surface opposite to each other and has at least one first conductive via. The rear surface of the image sensing element directly contacts the arc surface, and the first conductive via is extended from the front surface to the rear surface. In addition, a manufacturing method of the image sensor is also provided.
    Type: Grant
    Filed: December 25, 2018
    Date of Patent: March 9, 2021
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Wen Chiang, Hsiang-Hung Chang
  • Patent number: 10930668
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward Cho, Seok Hoon Kim, Myung Ii Kang, Geo Myung Shin, Seung Hun Lee, Jeong Yun Lee, Min Hee Choi, Jeong Min Choi
  • Patent number: 10930780
    Abstract: Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate and a plurality of raised active regions, wherein each raised active region is located on sidewalls of a corresponding semiconductor fin among said plurality of semiconductor fins. The raised active regions are laterally spaced from any other of the raised active regions. Each raised active region comprises angled sidewall surfaces that are not parallel or perpendicular to a topmost horizontal surface of said substrate. The raised active regions are silicon germanium (SiGe). The semiconductor structure includes a metal semiconductor alloy region contacting at least said angled sidewall surfaces of at least two adjacent raised active regions. The semiconductor alloy region includes a material selected from the group consisting of nickel silicide, nickel-platinum silicide and cobalt silicide.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: February 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Ahmet S. Ozcan
  • Patent number: 10923605
    Abstract: An optoelectronic apparatus is provided, comprising a carrier device that has a longitudinal extent and a transverse extent, wherein the carrier device has a plurality of electrically conductive tracks aligned in parallel with the longitudinal extent, and wherein the carrier device has a plurality of contact chambers aligned in parallel with the transverse extent at an upper side. Each of the contact tracks is electrically contactable in each contact chamber to be able to install at least one optoelectronic transmitter and/or at least one optoelectronic receiver in a variable mounting in the respective chamber.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: February 16, 2021
    Assignee: Vishay Semiconductor GmbH
    Inventors: Daniel Burger, Sascha Kuhn, Peter Mühleck
  • Patent number: 10916447
    Abstract: In a semiconductor device including a crystalline nitride layer, in which diamond is used for heat dissipation thereof, it is an object of the present invention to suppress cracking of the crystalline nitride layer. The semiconductor device includes a layered body and a heat dissipation layer. The layered body includes a crystalline nitride layer and a composite layer. The composite layer includes a non-inhibiting portion which does not inhibit diamond growth on a surface thereof and an inhibiting portion which inhibits the diamond growth on the surface. A layered body main surface of the layered body has a first region in which the non-inhibiting portion is exposed and a second region in which the inhibiting portion is exposed. The heat dissipation layer is made of diamond, opposed to the main surface, adhered to the first region, and separated from the second region with a void interposed therebetween.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: February 9, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasushi Fujioka, Takeo Furuhata, Tomohiro Shinagawa, Keisuke Nakamura
  • Patent number: 10910387
    Abstract: Disclosed is a semiconductor device including a first active pattern and a second active pattern that extend in a first direction on a substrate and are spaced apart from each other in a second direction crossing the first direction, a first gate structure that extends across the first and second active patterns, a second gate structure that is spaced apart from the first gate structure, and a node contact between the first and second gate structures that electrically connects the first active pattern and the second active pattern to each other. The node contact comprises a first end adjacent to the first active pattern and a second end adjacent to the second active pattern. The second end of the node contact being shifted in the first direction relative to the first end of the node contact so as to be closer to the second gate structure than to the first gate structure.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: February 2, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sangyoung Kim, Hyung Jong Lee, Deokhan Bae
  • Patent number: 10897026
    Abstract: To improve a degree of design freedom of a display surface of a device while maintaining a reliability of the device, provided is a display device including an active region that contributes to a display, and a notch formed in a position surrounded by an end portion of the active region. A protruding portion is formed on a peripheral end side of the active region where the notch is formed. A light-emitting layer is disconnected as a result of a step at the protruding portion.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: January 19, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kaoru Abe
  • Patent number: 10879432
    Abstract: Provided is a light emitting device package including: a light emitting device; a light transmitting plate body formed above the light emitting device and including a lower light transmitting plate, a plurality of side light transmitting plates formed on an upper surface of the lower light transmitting plate, an upper light transmitting plate corresponding to the upper surface of the lower light transmitting plate and formed on upper surfaces of the plurality of side light transmitting plates, and an empty portion formed inside; a wavelength converting unit including a first wavelength converting layer formed on a lower surface of the lower light transmitting plate and a second wavelength converting layer formed in the empty portion and covering the upper surface of the lower light transmitting plate; and an adhesive layer formed between the first wavelength converting layer and the light emitting device, in which the adhesive layer is formed on at least one side and an upper surface of the light emitting dev
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: December 29, 2020
    Assignee: LUMENS CO., LTD.
    Inventors: Seung Hyun Oh, Jung Hyun Park, Byeong Geon Kim, Pyoung Gug Kim, Sung Sik Jo, Jae Yoon Lim, Ho Joong Lim
  • Patent number: 10879248
    Abstract: A semiconductor device includes a substrate, a conductive pattern on the substrate, a lower electrode electrically connected to the conductive pattern, a dielectric layer covering a surface of the lower electrode, a first upper electrode on the dielectric layer, a diffusion barrier on an upper surface of the first upper electrode, and a second upper electrode covering the diffusion barrier, the second upper electrode including a different material from that of the first upper electrode.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoon-Sang Choi, Hyeok-Jin Jeong, Jung-Kun Lim, Young-Mo Tak, Sung-Kil Han
  • Patent number: 10879291
    Abstract: A three-dimensional (3D) stack is provided and includes a capacitor layer and an integrated circuit (IC) layer. The capacitor layer includes capacitors and capacitor layer connectors respectively communicative with corresponding capacitors. The IC layer is stacked vertically with the capacitor layer and is hybridized to a detector. The IC layer includes IC layer connectors respectively communicative with corresponding capacitor layer connectors.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: December 29, 2020
    Assignee: RAYTHEON COMPANY
    Inventors: Neil R. Malone, Sean P. Kilcoyne, Micky Harris
  • Patent number: 10867152
    Abstract: Thermal pattern sensor including a matrix of multiple rows and columns of pixels, each pixel comprising: - a pyroelectric capacitor comprising a pyroelectric portion positioned between lower and upper electrodes, in which a first of these electrodes forms a readout electrode; and —a heating element that is capable of heating the pyroelectric portion of said pixel; and in which: - for each row of pixels, the heating elements are capable of heating the pyroelectric portion of the pixels of the row independently of the heating elements of the pixels of the other rows; and —for each column of pixels, the readout electrodes of each pixel are electrically linked to one another and are formed by a first electrically conductive portion that makes contact with the pyroelectric portions of the pixels of the column, and that is separate from the first portions of the other columns.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 15, 2020
    Assignee: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Jean-François Mainguet, Joël Yann Fourre, Josep Segura Puchades