Abstract: A light source device includes a semiconductor light-emitting device which emits coherent excitation light, and a wavelength conversion element which is spaced from the semiconductor light-emitting device, generates fluorescence by converting the wavelength of the excitation light emitted from semiconductor light-emitting device, and generates scattered light by scattering the excitation light. The wavelength conversion element includes a support member, and a wavelength converter disposed on the support member. The wavelength converter includes a first wavelength converter, and a second wavelength converter which is disposed around the first wavelength converter to surround the first wavelength converter in a top view of the surface of the support member on which the wavelength converter is disposed. The ratio of the intensity of fluorescence to that of scattered light is lower in the second wavelength converter than in the first wavelength converter.

Abstract: A semiconductor device includes a fin structure protruding from a first isolation insulating layer provided over a substrate, a gate dielectric layer disposed over a channel region of the fin structure, a gate electrode layer disposed over the gate dielectric layer, a base semiconductor epitaxial layer disposed over a source/drain region of the fin structure, and a cap semiconductor epitaxial layer disposed over the base semiconductor epitaxial layer. The cap semiconductor epitaxial layer has a different lattice constant than the base semiconductor epitaxial layer, and a surface roughness of the cap semiconductor epitaxial layer along a source-to-drain direction is greater than zero and smaller than a surface roughness of the base semiconductor epitaxial layer along the source-to-drain direction.

Abstract: A quantum dot device including a first electrode and a second electrode each having a surface opposite the other, a quantum dot layer disposed between the first electrode and the second electrode, an electron transport layer disposed between the quantum dot layer and the second electrode and including first inorganic nanoparticles and a first organic material, and an electron injection layer disposed between the electron transport layer and the second electrode and including second inorganic nanoparticles and a second organic material, wherein a ratio by weight of an amount of the second organic material to a total amount of the second inorganic nanoparticles and the second organic material in the electron injection layer is less than a ratio by weight of an amount of the first organic material to a total amount of the first inorganic nanoparticles and the first organic material in the electron transport layer. An electronic device including the quantum dot device.

Abstract: In EL display panels fabricated by vapor deposition, a vapor-deposition fine mask is employed to form red, green, and blue pixels. An issue, however, has been that misregistration of the vapor-deposition fine mask occurs, lowering manufacturing yields. To resolve this issue, on a thin-film transistor (TFT) substrate, red, green, and blue pixel electrodes are fashioned in matrix form. The TFT substrate is conveyed into a vapor-deposition chamber. Under a vacuum, an organic evaporation source is employed to codeposit a light-emitting layer composed of a host material and a red guest material on the TFT substrate display screen. An ultraviolet laser beam generated by a laser device is optically guided into the vapor-deposition chamber through a laser window and directed on the light-emitting layer formed onto the green and blue pixel electrodes. Positional selecting on the green and blue pixels is carried out by controlling a mirror galvanometer.

Abstract: A display substrate includes: a base substrate including a display area and a peripheral area pixel units in the display area, each including a pixel drive circuit and a light emitting device the light emitting device including a first electrode, a second electrode, and a light emitting layer; a first power trace located in the peripheral area and electrically connected to the first electrode; a second power trace located in the peripheral area and electrically connected to the second electrode; a planarization layer with at least a portion thereof being located in the peripheral area. An orthographic projection of the planarization layer on the base substrate at least partially overlaps an orthographic projection of each of the first and second power traces on the base substrate, the first and second power traces are located in different layers, and a portion of the planarization layer is located between the first and second power traces.

Abstract: In one aspect, a method of fabricating a transistor includes depositing a first epitaxial layer; depositing a second epitaxial layer on the first epitaxial layer; forming a single termination trench in the second epitaxial layer; and filling the termination trench with a dielectric. A depth of the termination trench is greater than 10 microns. In another aspect, a transistor includes a first epitaxial layer; a second epitaxial layer on the first epitaxial layer; and a single termination trench in the second epitaxial layer. The termination trench is greater than 10 microns and is filled with a dielectric.

Abstract: A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

Abstract: A heterojunction electronic component includes a substrate; a heterojunction including a channel layer arranged on the substrate and a barrier layer arranged on the channel layer; a passivation layer arranged on the barrier layer; a field plate separated from the barrier layer by a portion of the passivation layer; and a floating region made from a p-doped semiconductor material, located in the barrier layer in vertical alignment with a flank of the field plate, the floating region having a thickness less than that of the barrier layer.

Abstract: A semiconductor device has a first and a second nitride semiconductor layer and a first and a second electrode thereon. A gate electrode is between the first and second electrodes. A gate field plate is on the gate electrode. A first field plate is above a position between the gate field plate and the second electrode. A second field plate is between the first field plate and the gate field plate. A distance from the first nitride semiconductor layer to the second field plate is shorter than a distance from the first nitride semiconductor layer to the portion of the gate field plate that protrudes the most towards the second electrode. The distance from the first nitride semiconductor layer to the second field plate is shorter than a distance from the first nitride semiconductor layer to an end surface of the first field plate on a first electrode side.

Abstract: A memory device including bit lines, auxiliary lines, selectors, and memory cells is provided. The word lines are intersected with the bit lines. The auxiliary lines are disposed between the word lines and the of bit lines. The selectors are inserted between the bit lines and the auxiliary lines. The memory cells are inserted between the word lines and the auxiliary lines.

Abstract: A semiconductor device including a well region in a substrate, an impurity region in the well region, a first active fin on the impurity region, a second active fin on the well region, and a connection pattern penetrating the second active fin and connected to the well region may be provided. The substrate and the impurity region include impurities having a first conductivity type. The well region includes impurities having a second conductivity type different from the first conductivity type. The first active fin includes a plurality of first semiconductor patterns that are spaced apart from each other in a direction perpendicular to a top surface of the substrate. The first semiconductor patterns and the impurity region include impurities having the first conductivity type.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to improved turn-on voltage of high voltage electrostatic discharge device and methods of manufacture. The structure comprises a high voltage NPN with polysilicon material on an isolation structure located at a base region, the polysilicon material extending to at least one of a collector and emitter of a bipolar junction transistor (BJT), and the polysilicon material completely covering the base region of the BJT.

Abstract: A semiconductor device includes a semiconductor layer, a first electrode on a first surface of the semiconductor layer, a plurality of second electrodes on a second surface of the semiconductor layer, a control electrode between the first electrode and each of the plurality of second electrodes and electrically insulated from the semiconductor layer and each of the plurality of second electrodes, and a resin layer partially covering the second surface of the semiconductor layer and having a plurality of openings through which the respective second electrodes are at least partially exposed. Each of the plurality of openings has rounded corners. The device further includes a sensor element above the second surface of the semiconductor layer and covered by a first part of the resin layer surrounded by the openings.

Abstract: A reflective layer for use in lighting devices and methods of forming the reflective layer are provided. The reflective layer may include a dielectric layer including one or more insulating materials. An intermediate layer may be formed on the dielectric layer. The intermediate layer may include one or more materials having a higher enthalpy of reaction than the one or more insulating materials. Because of the higher enthalpy of reaction, atoms of the one or more materials in the intermediate layer may form bonds with atoms of the one or more insulating materials. A metal layer may be formed on the intermediate layer to reflect light emitted from an active region of a light emitting diode (LED).

Abstract: The present disclosure describes a metal-oxide-semiconductor field-effect transistor (MOSFET) device. The MOSFET device includes a first-type substrate, a deep-second-type well in the first-type substrate, a first-type well over the deep-second-type well, and a second-type well over the deep-second-type well. The second-type well and the deep-second-type well form an enclosed space that includes the first-type well. The MOSFET also includes an embedded semiconductor region (ESR) in a vicinity of the enclosed space. The ESR includes a dopant concentration lower than at least one of a dopant concentration of the first-type well, a dopant concentration of the second-type well, and a dopant concentration of the deep-second-type well.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region within a semiconductor substrate material; a shallow trench isolation structure extending into the semiconductor substrate material and bounding the extrinsic base region; an emitter region adjacent to the shallow trench isolation structure and on a side of the extrinsic base region; and a collector region adjacent to the shallow trench isolation structure and on an opposing side of the extrinsic base region.

Abstract: A disclosed structure includes a fin-based bipolar junction transistor (BJT) with reduced base resistance. The BJT includes one or more semiconductor fins. Each semiconductor fin has opposing sidewalls, a first width, and a base recess, which extends across the first width through the opposing sidewalls. The BJT includes a base region positioned laterally between collector and emitter regions. The base region includes a base semiconductor layer (e.g., an intrinsic base layer), which fills the base recess and which has a second width greater than the first width such that the base semiconductor layer extends laterally beyond the opposing sidewalls. In a BJT with multiple semiconductor fins, the base recess on each semiconductor fin is filled with a discrete base semiconductor layer. The base region further includes an additional base semiconductor layer (e.g., an extrinsic base layer) covering the base semiconductor layer(s). Also disclosed is a method of forming the structure.

Abstract: A power diode comprises a plurality of diode cells (10). Each diode cell (10) comprises a first conductivity type first anode layer (40), a first conductivity type second anode layer (45) having a lower doping concentration than the first anode layer (40) and being separated from an anode electrode layer (20) by the first anode layer (40), a second conductivity type drift layer (50) forming a pn-junction with the second anode layer (45), a second conductivity type cathode layer (60) being in direct contact with the cathode electrode layer (60), and a cathode-side segmentation layer (67) being in direct contact with the cathode electrode layer (30). A material of the cathode-side segmentation layer (67) is a first conductivity type semiconductor, wherein an integrated doping content of the cathode-side, which is integrated along a direction perpendicular to the second main side (102), is below 2·1013 cm?2, or a material of the cathode-side segmentation layer (67) is an insulating material.

Abstract: The disclosure provides a bipolar transistor structure with multiple bases, and related methods. A bipolar transistor structure includes a first emitter/collector (E/C) material above an insulator. The first E/C material has first sidewall and a second sidewall over the insulator. A first base is above the insulator adjacent the first sidewall of the first E/C material. A second base is above the insulator adjacent the second sidewall of the first E/C material. A second E/C material is above the insulator and adjacent the first base. A width of the first base between the first E/C material and the second E/C material is less than a width of the first E/C material, and the first base protrudes horizontally outward from an end of the first E/C material and an end of the second E/C material.