Abstract: A display panel and a method for manufacturing same are provided. The display panel includes a light emitting device layer and a light filter layer. The light filter layer is arranged on a light-emitting side of the light emitting device layer. The light filter layer includes color resists and a light-shielding layer adjacently arranged. Each color resist has an extension portion, and the extension portion of the color resist is stacked and arranged in a pixel spacer portion of the display panel to form the light-shielding layer. Therefore, a laminated structure which can effectively prevent color shifts of light emitted from inside of the display panel is provided, thereby improving display effect of the display panel.

Abstract: Power semiconductor device with reduced loss and manufacturing method the same disclosed. Power semiconductor device include a first drift region of a first conductivity type, a second drift region of the first conductivity type formed by epitaxially growing on the first drift region and a plurality of buried ion regions of a second conductivity type formed to be buried in the second drift region.

Abstract: A display device according to an embodiment of the present invention includes a display panel having a through hole in a display area including a plurality of pixels. The display panel includes a substrate, and an organic light-emitting diode including a first electrode provided above the substrate for each of the pixels, a second electrode provided over the plurality of pixels, and an organic electroluminescence layer arranged between the first electrode and the second electrode. The through hole penetrates at least the second electrode, and the second electrode includes an oxidized part exposed at an inner surface of the through hole.

Abstract: Integrated circuit devices may include: a gate stack extending on a substrate in a first direction that may be parallel to a main surface of the substrate, the gate stack including a plurality of gate electrodes overlapping each other in a vertical direction that may be perpendicular to the main surface of the substrate; a channel structure extending through the gate stack and extending in the vertical direction; a word line cut opening extending through the gate stack in the vertical direction and extending in the first direction; and an upper support layer on the gate stack and including a hole overlapping the word line cut opening in the vertical direction. An upper surface of the channel structure is in contact with a lower surface of the upper support layer.

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.

Abstract: A light-emitting element includes: a semiconductor stack having a triangular shape in a top plan view, the semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first and seconds semiconductor layers; a first electrode located on the first semiconductor layer and including a first connecting portion and a first extension extending from the first connecting portion; and a second electrode located on the second semiconductor layer and including a second connecting portion and a second extension extending from the second connecting portion. The first extension includes a first portion extending from the first connecting portion toward the second connecting portion. The second extension includes a second portion including a portion extending along a first side, a third portion including a portion extending along a second side, and fourth and fifth portions each including a portion extending along a third side.

Abstract: Disclosed semiconductor structure embodiments include a bipolar junction device configured to have a high holding voltage. The device includes base, collector and emitter terminals. The high holding voltage is achieved because of a uniquely configured emitter terminal. Specifically, the device includes a base well region, which has a first-type conductivity. The emitter terminal includes, adjacent to the base well region (e.g., within and/or on the base well region), an emitter contact region, which has a second-type conductivity, and an ancillary emitter region, which abuts the emitter contact region and which has the first-type conductivity at a higher conductivity level than the base well region. Embodiments vary with regard to the shapes of the emitter contact region and ancillary emitter region. Embodiments also vary with regard to the structures used to isolate the collector terminal from the emitter terminal and with regard to the areas covered by silicide layers.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: In one embodiment, an asymmetric TVS device may include a semiconductor substrate, comprising an inner region, the inner region having a first polarity, and a first surface region, disposed on a first surface of the semiconductor substrate, the first surface region comprising a second polarity, opposite the first polarity. The asymmetric TVS device may also include a second surface region, comprising the second polarity, and disposed on a second surface of the semiconductor substrate, opposite the first surface, wherein the first surface region comprises a first dopant concentration, and wherein the second surface region comprises a second dopant concentration, greater than the first dopant concentration.

Abstract: A vertical current mode solid state device comprising a connection pad and side walls comprising a metal-insulator-semiconductor (MIS) structure, wherein leakage current effect of the vertical device is limited through the side walls by biasing the MIS structure.

Abstract: A laminated body is provided in a circumferential shape with a gap formed in a part of a circumferential direction on a semiconductor layer. In the laminated body, a first insulating layer, a gate layer, a second insulating layer, and a drain layer are layered in this order from the semiconductor layer side. An impurity diffusion layer is formed on a surface of the semiconductor layer, and a backside electrode on a backside surface. The impurity diffusion layer extends from a position in contact with side walls in a channel space to an outside of the laminated body through a region corresponding to the gap on the surface of the semiconductor layer. A portion of the impurity diffusion layer beyond the laminated body is a contact region to which a wiring for applying a predetermined voltage is connected. A cover layer made of an insulating material is formed in an upper portion and a periphery of the annular portion including the laminated body and the gap.

Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region.

Abstract: A semiconductor device manufacturing method includes: forming a first groove having depth H in a semiconductor layer; filling the first groove with an oxide film and forming a surface oxide film having thickness a on an upper surface of the semiconductor layer to equalize the oxide film and the surface oxide film in height; forming a second groove having depth h greater than thickness a, from an uppermost surface of a third oxide film; forming gate trenches deeper than depth H, in the semiconductor layer; depositing polysilicon until at least the gate trenches and the second groove are filled with polysilicon; forming a peripheral element by injecting an impurity into polysilicon deposited in the second groove; and making a thickness of the peripheral element equal to depth h by concurrently removing polysilicon deposited in the gate trenches and polysilicon deposited in the second groove until they become equal in height.

Abstract: A method for forming a semiconductor Schottky rectifier device includes providing a semiconductor substrate, forming a hard mask for trench etch including openings for guard rings, an anode region, and a cathode region, and etching semiconductor epitaxial material layer to form a plurality of trenches. The method also includes forming a first dielectric layer and depositing a polysilicon layer, performing an anisotropic etch of the polysilicon layer to form polysilicon elements on sidewalls of the trench, and depositing and etching a second dielectric layer to expose a Schottky diode region and a bottom region of the trench in the cathode region. The method further includes depositing a first metal layer and performing a thermal treatment to form metal silicide in the Schottky diode region and the cathode region and forming a second metal layer and separating the second metal layer into an anode electrode and a cathode electrode.

Abstract: A high electron mobility transistor includes an epitaxial stack on a substrate, a gate structure on the epitaxial stack, a passivation layer on the epitaxial stack and covering the gate structure, and an air gap between the passivation layer and the gate structure.

Abstract: A display device includes a plurality of islands and a bridge connecting the plurality of islands to each other. Each of the plurality of islands includes a flexible substrate, a thin film transistor positioned on a first surface of the flexible substrate, a first electrode connected to the thin film transistor, and a protective mask positioned on a second surface of the flexible substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a stack of word line layers and insulating layers that are stacked alternatingly over a substrate. The semiconductor device also includes a first dielectric trench structure. The first dielectric trench structure is positioned in a bottom select gate (BSG) layer of the word line layers to separate the BSG layer and extends in a first direction of substrate. The semiconductor device further includes a second dielectric trench structure. The second dielectric trench structure is positioned in a top select gate (TSG) layer of the word line layers to separate the TSG layer and extends in the first direction of the substrate. The second dielectric trench structure is offset from the first dielectric trench structure in a second direction of the substrate that is perpendicular to the first direction.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base having at least one sidewall with a gradient concentration of semiconductor material; an emitter on a first side of the extrinsic base; and a collector on a second side of the extrinsic base.

Abstract: A method of manufacturing a semiconductor device comprises steps of: forming a semiconductor stack by growing an AlGaN layer or an InAlN layer, an AlN layer, and a GaN layer on a substrate in this order; forming a recess in the semiconductor stack by a dry etching from a surface of the semiconductor stack, the surface being opposite to the substrate; growing a GaN region in the recess; and forming an ohmic electrode on the GaN region; wherein in the forming of the recess, the dry etching is stopped in response to the recess reaching the AlN layer.

Abstract: A semiconductor device that can detect temperature appropriately is provided. A semiconductor device provided with a semiconductor substrate in which one or more transistor portions and one or more diode portions are provided is provided, including: a temperature detecting portion provided above the top surface of the semiconductor substrate and having a longitudinal side in a predetermined longitudinal direction; a top surface electrode provided above the top surface of the semiconductor substrate; and one or more external lines that have a connecting part connected with the top surface electrode and electrically connect the top surface electrode to a circuit outside the semiconductor device. The temperature detecting portion extends across the one or more transistor portions and the one or more diode portions in the longitudinal direction, and the connecting part of at least one of the external lines is arranged around the temperature detecting portion when seen from above.