Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.

Abstract: A nonvolatile memory device according to an embodiment of the present disclosure includes a substrate having a channel layer, a first tunneling layer disposed on the channel layer, a second tunneling layer disposed on the first tunneling layer, a third tunneling layer disposed on the second tunneling layer, a charge trap layer disposed on the third tunneling layer, a charge barrier layer disposed on the charge trap layer, and a gate electrode layer disposed on the charge barrier layer. The first tunneling layer includes a first insulative material. The second tunneling layer includes a second insulative material. The third tunneling layer includes a second insulative material. The resistance switching material is a material whose electric resistance varies reversibly between a high resistance state and a low resistance state depending on a magnitude of an applied electric field.

Abstract: A semiconductor device includes a channel layer, a barrier layer, source contact and a drain contact, a doped group III-V layer, and a gate electrode. The barrier layer is positioned above the channel layer. The source contact and the drain contact are positioned above the barrier layer. The doped group III-V layer is positioned above the barrier layer and between the first drain contact and the first source contact. The first doped group III-V layer has a first non-vertical sidewall and a second non-vertical sidewall. The gate electrode is positioned above the doped group III-V layer and has a third non-vertical sidewall and a fourth non-vertical sidewall. A horizontal distance from the first non-vertical sidewall to the third non-vertical sidewall is different than a horizontal distance from the second non-vertical sidewall to the fourth non-vertical sidewall.

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

Abstract: An integrated circuit device includes a first-type active-region semiconductor structure, a first gate-conductor, a second-type active-region semiconductor structure that is stacked with the first-type active-region semiconductor structure, and a second gate-conductor. The integrated circuit device also includes a front-side conductive layer above the two active-region semiconductor structures and a back-side conductive layer below the two active-region semiconductor structures. The integrated circuit device also includes a front-side power rail and a front-side signal line in the front-side conductive layer and includes a back-side power rail and a back-side signal line in the back-side conductive layer. The integrated circuit device also includes a first source conductive segment connected to the front-side power rail and a second source conductive segment connected to the back-side power rail.

Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.

Abstract: A magnetoresistive random access memory (MRAM) device and a method of manufacturing the same, the device including a substrate; a memory unit including a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked on the substrate; a passivation pattern on a sidewall of the memory unit; a via on the memory unit and contacting the upper electrode; and a wiring on the via and contacting the via, wherein a center portion of the upper electrode protrudes from a remaining portion of the upper electrode in a vertical direction substantially perpendicular to an upper surface of the substrate.

Abstract: A lighting module according to an embodiment of the invention includes: a substrate; a plurality of light emitting devices disposed in N rows (N is an integer of 1 or more) on the substrate; a first resin layer covering the plurality of light emitting devices; a first diffusion layer disposed on the first resin layer and diffusing light emitted from the first resin layer; and a second diffusion layer disposed on the first diffusion layer and diffusing light emitted from the first diffusion layer, wherein the first diffusion layer includes a diffusing agent, and the second diffusion layer includes at least one of a phosphor and ink particles.

Abstract: Embodiments of this application disclose a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate and having a first bandgap, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a second bandgap. The second bandgap is larger than the first bandgap. The semiconductor device further includes a gate contact disposed over the second nitride semiconductor layer and a first field plate disposed over the gate contact. The first field plate has a first surface facing the substrate, a second surface facing the substrate, and a protruded portion. The protruded portion has a bottom surface facing the substrate. The bottom surface is located between the first surface and the second surface.

Abstract: A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.

Abstract: A memory cell includes a thin film transistor over a semiconductor substrate, the thin film transistor including: a memory film contacting a word line; and an oxide semiconductor (OS) layer contacting a source line and a bit line, wherein the memory film is disposed between the OS layer and the word line, wherein the source line and the bit line each comprise a first conductive material touching the OS layer, and wherein the first conductive material has a work function less than 4.6. The memory cell further includes a dielectric material separating the source line and the bit line.

Abstract: A method of forming an alignment contact includes: providing a III-nitride substrate; epitaxially growing a first III-nitride layer on the III-nitride substrate, wherein the first III-nitride layer is characterized by a first conductivity type; forming a plurality of III-nitride fins on the first III-nitride layer, wherein each the plurality of III-nitride fins is separated by one of a plurality of first recess regions, wherein the plurality of III-nitride fins are characterized by the first conductivity type; epitaxially regrowing a III-nitride source contact portion on each of the plurality of III-nitride fins; and forming a source contact structure on the III-nitride source contact portions.

Abstract: Aspects of the disclosure provide a bipolar transistor structure with a sub-collector on a substrate, a first collector region on a first portion of the sub-collector, a trench isolation (TI) on a second portion of the sub-collector and adjacent the first collector region, and a second collector region on a third portion of the sub-collector and adjacent the TI. A base on first collector region and a portion of the TI. An emitter is on a first portion of the base above the first collector region. The base includes a second portion horizontally displaced from the emitter in a first horizontal direction, and horizontally displaced from the second collector region in a second horizontal direction orthogonal to the first horizontal direction.

Abstract: A high electron mobility transistor (HEMT) includes a channel layer comprising a group III-V compound semiconductor; a barrier layer comprising the group III-V compound semiconductor on the channel layer; a gate electrode on the barrier layer; a source electrode over gate electrode; a drain electrode spaced apart from the source electrode; and a metal wiring layer. A same layer of the metal wiring layer includes a gate wiring connected to the gate electrode, a source field plate connected to the source electrode, and a drain field plate connected to the drain electrode.

Abstract: The semiconductor storage device of an embodiment includes a first conductive layer, a stack disposed above the first conductive layer and including a plurality of second conductive layers in a first direction, and a columnar body that extends in the first direction through the stack, and includes a semiconductor layer and a charge storage film provided between the plurality of conductive layers and the semiconductor layer. A first conductive layer out of the plurality of conductive layers is connected to the semiconductor layer, and the semiconductor layer includes a first region in which a concentration of an n-type impurity is higher than a concentration of a p-type impurity, a second region in which a concentration of a p-type impurity is higher than a concentration of an n-type impurity, and a third region contacted to the first conductive layer and disposed closer to the first region than the second region in the first direction.

Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.

Abstract: Transistors having reduced parasitics and enhanced performance. In some embodiments, a transistor can include a source and a drain each implemented as a first type active region, and a gate implemented relative to the source and the drain such that application of a voltage to the gate results in formation of a conductive channel between the source and the drain. The transistor can further include a body configured to provide the conductive channel upon the application of the voltage to the gate. The body can be implemented as a second type active region that butts with the first type active region on the source side at a respective area not covered by the gate, and does not butt with the first type active region on the drain side at a respective area not covered by the gate.

Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.

Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.