Abstract: A light emitting display device according to an exemplary embodiment of the present disclosure includes: a first substrate; an insulating layer disposed on the first substrate and having an inclined portion; a first electrode disposed on the insulating layer; a light-emitting layer disposed on the first electrode; a second electrode disposed on the light-emitting layer; and a plurality of color conversion layers disposed on the second electrode. The first electrode includes an inclined portion that is inclined along the inclined portion of the insulating layer based on a surface parallel to the first substrate, and the light-emitting layer includes semiconductor nano-particles.

Abstract: Described herein is a semiconductor structure and method of manufacture. The semiconductor structure includes a plurality of semiconductor fins on a substrate and a plurality of raised active regions, wherein each raised active region is located on sidewalls of a corresponding semiconductor fin among said plurality of semiconductor fins. The raised active regions are laterally spaced from any other of the raised active regions. Each raised active region comprises angled sidewall surfaces that are not parallel or perpendicular to a topmost horizontal surface of said substrate. The raised active regions are silicon germanium (SiGe). The semiconductor structure includes a metal semiconductor alloy region contacting at least said angled sidewall surfaces of at least two adjacent raised active regions. The semiconductor alloy region includes a material selected from the group consisting of nickel silicide, nickel-platinum silicide and cobalt silicide.

Abstract: A SiC MOSFET device having low specific on resistance is described. The device has N+, P-well and JFET regions extended in one direction (Y-direction) and P+ and source contacts extended in an orthogonal direction (X-direction). The polysilicon gate of the device covers the JFET region and is terminated over the P-well region to minimize electric field at the polysilicon gate edge. In use, current flows vertically from the drain contact at the bottom of the structure into the JFET region and then laterally in the X direction through the accumulation region and through the MOSFET channels into the adjacent N+ region. The current flowing out of the channel then flows along the N+ region in the Y-direction and is collected by the source contacts and the final metal. Methods of making the device are also described.

Abstract: A light-emitting device in which the emission intensity of light-emitting elements is improved by making heat generated by light emission of the light-emitting elements be effectively released is provided. The light-emitting device includes a mounting substrate including a mounting region, light-emitting elements mounted on the mounting region, a sealing resin which contains a phosphor and integrally seals the light-emitting elements, and at least one heat transfer member which is arranged among the light-emitting elements on the mounting region, is embedded in the sealing resin, and has a higher thermal conductivity than the sealing resin.

Abstract: Disclosed is an optoelectronic semiconductor component (1) comprising a semiconductor member (2) that has a succession of semiconductor layers including an active region (20) for generating radiation, a first semiconductor layer (21), and a second semiconductor layer (22). The active region is located between the first semiconductor layer and the second semiconductor layer; the semiconductor member has a plurality of cavities (25) which extend through the second semiconductor layer and the active region; and from a bird's eye view onto the semiconductor member, the cavities are elongate and have a longitudinal axis (250).

Abstract: Provided is a display panel, including an array substrate and a color film substrate; in the array substrate, every two adjacent columns of highlight sub-pixels form a group of highlight sub-pixels, at least one column of color sub-pixels is arranged between any two groups of highlight sub-pixels; the color film substrate includes a black matrix and color filters arranged in array, the black matrix includes a first and second black matrixes, the color filter includes columns of highlight color filters and columns of colored color filters, every two adjacent columns of highlight color filters form a group of highlight color filters, at least one column of colored color filters is arranged between any two groups of highlight color filters; on the color film substrate, orthogonal projection of the second black matrix does not overlap with orthogonal projection of the gap between the two adjacent columns of highlight color filters.

Abstract: The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.

Abstract: In an LED module, modes to solve such a problem that a loss in the output of light discharged into the atmosphere occurs are embodied. Specifically, in an LED module in which an LED chip is sealed with a sealing resin, a surface of the sealing resin is covered with a thin film, the thin film is made of a material having a smaller linear expansion coefficient than the sealing resin, and an irregular surface is provided on a surface of the thin film such that light from the LED chip is multiply reflected.

Abstract: Provided herein is a method including forming a cavity in a first side of a first silicon wafer. An oxide layer is formed on the first side and in the cavity. The first side of the first silicon wafer is bonded to a first side of a second silicon wafer, and a gap control structure is deposited on a second side of the second silicon wafer. A MEMS structure is formed in the second silicon wafer. The second side of the second silicon wafer is eutecticly bonded to the third silicon wafer, and the eutectic bonding includes pressing the second silicon wafer to the third silicon wafer.

Abstract: Provided is a magnetic shield having improved shielding properties from an external magnetic field. A magnetic shield MS1 has in-plane magnetization as remanent magnetization, and is adapted to generate a perpendicular component in the magnetization direction by applying a magnetic field in the perpendicular direction to the magnetic shield.

Abstract: Embodiments of a device are provided, including a semiconductor substrate including an active device area; a body region disposed in the semiconductor substrate within the active device area, wherein a channel is formed within the body region during operation; a doped isolation layer disposed in the semiconductor substrate underneath the active device area, the doped isolation layer including an opening positioned under the active device area; and a lightly-doped isolation layer disposed in the semiconductor substrate underneath the active device area, the lightly-doped isolation layer positioned at least within the opening and in electrical contact with the doped isolation layer, wherein the doped isolation layer and the lightly-doped isolation layer form a doped isolation barrier that extends across an entire lateral extent of the active device area.

Abstract: A wiring pattern manufacturing method includes: applying a liquid body including a first formation material on a substrate to form a base film; applying a liquid body including a second formation material on at least part of a surface of the base film to form a protection layer of the base film; forming a resist layer on a surface of the protection layer to expose the resist layer with desired patterning light; causing the exposed resist layer to come into contact with a developer to remove the resist layer and the protection layer until the base film is uncovered corresponding to the patterning light; and after depositing a catalyst on a surface of the uncovered base film, causing an electroless plating solution to come into contact with the surface of the base film to perform electroless plating.

Abstract: Provided is a transistor which includes an oxide semiconductor film in a channel region. A change from a shift value before light irradiation to a shift value under light irradiation is greater than or equal to ?1 V and less than or equal to 0.5 V, where the shift value is a gate voltage at a point of intersection of an axis of 1×10?12 A and a steepest tangent line of the logarithm of a drain current in drain current-gate voltage characteristics of the transistor, and where the light irradiation is performed on the oxide semiconductor film with light having an energy greater than or equal to a band gap of the oxide semiconductor film.

Abstract: Disclosed is a thin film transistor including both an N-type semiconductor layer and a P-type semiconductor layer, a method for manufacturing the same, and a display device including the same, wherein the thin film transistor may include a first gate electrode on a substrate; a first gate insulating film covering the first gate electrode; a semiconductor layer on the first gate insulating film; a second gate insulating film covering the semiconductor layer; and a second gate electrode on the second gate insulating film, wherein the semiconductor layer includes the N-type semiconductor layer and the P-type semiconductor layer.

Abstract: A nanoelectronic system comprised of n microelectromechanical or nanoelectromechanical devices arranged on a connection support to electrically connect the n devices, each device with an interaction area, at least one mechanical anchor and a first terminal, a second terminal and a third terminal, the relative arrangement of the first, second and third terminals, the anchor area and the interaction area being identical or similar for the n sensors, the first terminal of each device being intended to recover a signal emitted by each representative device of the interaction area state. At least part of the devices are arranged in such a way that the geometric location of the first terminal of one of the adjacent devices is identical to the geometric location of the first terminal of said other adjacent device, the first terminals being coincident.

Abstract: A memory device including a substrate, at least one first stacked structure and at least one second stacked structure disposed on the substrate is provided. The first stacked structure includes a plurality of alternately stacked metal layers and oxide layers. The second stacked structure is disposed adjacent to the first stacked structure and includes a plurality of alternately stacked semiconductor layers and oxide layers. The metal layers of the first stacked structure are connected to the semiconductor layers of the second stacked structure.

Abstract: In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

Abstract: A LED flip-chip package substrate includes a ceramic base (e.g., aluminum nitride base), a conductive wire layer disposed on the ceramic base and having pads in pairs, an insulating protective layer (e.g., low-temperature glass glaze layer) disposed on a same side of the ceramic base as the conductive wire layer and exposing the pads, and a metallic reflective layer (e.g., aluminum layer) disposed on a side of the insulating protective layer facing away from the ceramic base and exposing the pads. Moreover, a LED package structure adopting the LED flip-chip package substrate and other LED package structures with similar material layers such as a chip-level packaged LED package structure are provided. By comprehensively utilizing advantages of various materials, the LED flip-chip package substrate with high heat conductivity, high reflectivity, high stability and superior insulation and the LED package structure with high reliability and even high light extraction efficiency are obtained.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack and a second gate stack over a substrate. Each of them has gate spacers disposed along its respective sidewalls. The method also includes forming a source/drain (S/D) feature disposed between the first and second gate stacks. The gate spacers and a top surface of the S/D feature define a space. The method also includes forming a first dielectric layer over the S/D feature in the space, forming a capping layer along the gate spacers in the space, forming a second dielectric layer over the first dielectric layer in the space and forming a contact trench extending through the second dielectric layer, the first dielectric layer and the capping layer to expose the top surface of the S/D feature.

Abstract: An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a fin. The insulators are located over the substrate, wherein the fin is located between the insulators. The floating gate is located over the fin and the insulators. The control gate is located over the floating gate on the insulators and includes at least one of first contact slots located over the sidewalls of the floating gate.