Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.

Abstract: A semiconductor structure is provided in which an nFET nanosheet stack of suspended silicon channel material nanosheets is present in an nFET device region and a pFET nanosheet stack of suspended silicon germanium alloy channel material nanosheets is present in a pFET device region. The silicon channel material nanosheets of the nFET nanosheet stack are off-set by one nanosheet from the silicon germanium alloy channel material nanosheets of the pFET nanosheet stack.

Abstract: A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes introducing an impurity to a rear surface of a semiconductor substrate, performing first heat treating to activate the impurity to form a field stop layer, performing a first irradiation to irradiate light ions from the rear surface of semiconductor substrate to form, in the semiconductor substrate, a first low-lifetime region, performing a second irradiation to irradiate the light ions from the rear surface of the semiconductor substrate to form, in the field stop layer, a second low-lifetime region, and performing second heat treating to reduce a density of defects generated in the field stop layer when the second irradiation is performed. Each of the first and second low-lifetime regions has a carrier lifetime thereof shorter than that of any region of the semiconductor device other than the first and second low-lifetime regions.

Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film.

Abstract: A magnetic junction, a memory using the magnetic junction and method for providing the magnetic junction are described. The magnetic junction resides on a substrate and is usable in a magnetic device. The magnetic junction includes a reference layer, a nonmagnetic spacer layer and a M-containing oxide layer adjacent to the free layer. M includes at least one of Ti, Al, Hf, Zr, Mo, V and Nb. The free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. The nonmagnetic spacer layer is between the reference layer and the free layer. The free layer is between the nonmagnetic spacer layer and the M-containing oxide layer.

Abstract: Semiconductor devices and methods for making the same include patterning a stack of layers that includes channel layers, first sacrificial layers between the channel layers, and second sacrificial layers between the channel layers and the first sacrificial layers, to form one or more device regions. The first sacrificial layers are formed from a material that has a same lattice constant as a material of the first sacrificial layers and the second sacrificial layers are formed from a material that has a lattice mismatch with the material of the first sacrificial layers. Source and drain regions are formed from sidewalls of the channel layers in the one or more device regions. The first and second sacrificial layers are etched away to leave the channel layers suspended from the source and drain regions. A gate stack is deposited on the channel layers.

Abstract: A display device includes a display area, a peripheral area, a pad portion, a bending area, a first crack detection circuit, and a first crack detection line. The display area includes pixels and data lines. The peripheral area is disposed outside the display area. The pad portion is disposed in the peripheral area. The bending area is disposed in the peripheral area. The bending area is bendable or in a bent state. The first crack detection circuit is disposed between the display area and the pad portion. The first crack detection circuit includes switches. The first crack detection line includes a first curved portion disposed in the bending area. The first crack detection line is connected between the pad portion and the first crack detection circuit.

Abstract: A semiconductor device includes a stack of layers stacked vertically and including a source layer, a drain layer and a channel layer between the source layer and the drain layer. A gate electrode is formed in a common plane with the channel layer and a gate dielectric is formed vertically between the gate electrode and the channel layer. A first contact contacts the stack of layers on a first side of the stack of layers, and a second contact formed on an opposite side vertically from the first contact.

Abstract: An integrated circuit includes a first and a second field effect transistor structure. The first field effect transistor structure includes a first gate electrode structure and a first field electrode structure. The second field effect transistor structure includes a second gate electrode structure and a second field electrode structure. The first and the second gate electrode structures are electrically separated from each other. The first and the second field electrode structures are separated from each other.

Abstract: A storage device includes a first electrode, a stacked feature, a spacer and a barrier structure. The stacked feature is position over the first electrode, and includes a storage element and a second electrode over the storage element. The spacer is positioned on a sidewall of the stacked feature, the spacer having a notch positioned on a top surface of the spacer, in which the notch of the spacer has a surface which is continuous with a top surface of the stacked feature. The barrier structure is embedded in a lateral of the spacer. The barrier structure has a top extending upwards past a bottom of the notch.

Abstract: An image sensor may include an array of pixels having a color filter layer. The color filter layer may include colored elements and clear elements. The clear elements may be formed from transparent dielectric material. The color filter layer may include a grid of light-blocking material that forms color filter container structures having an array of openings in which the colored elements and the clear elements are formed. The color filter container structures may be formed from the same transparent dielectric material that forms the clear elements. The color filter container structures may be formed from opaque materials or transparent materials that form structures such as planarization layers, microlenses, or antireflection coatings for the array of pixels. The material used to form the color filter container structures may have a refractive index that is sufficiently high to prevent light from passing between adjacent elements in the color filter layer.

Abstract: A method of producing a semiconductor device according to an embodiment of the present invention includes: step (C) of forming an oxide semiconductor layer of a plurality of thin film transistors on a gate dielectric layer; step (F) of forming an aperture in an interlevel dielectric layer, the aperture being located between an active region and a plurality of terminal portions and extending through the interlevel dielectric layer; and step (G) of, after step (F), forming an upper conductive portion on the interlevel dielectric layer. In step (C), a protection layer made of the same oxide semiconductor film as the oxide semiconductor layer is formed above a region of the gate dielectric layer that is located between the active region and the plurality of terminal portions. In step (F), the aperture is formed so as to overlap the protection layer.

Abstract: A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.

Abstract: A method for manufacturing a plurality of light emitting elements includes: providing a semiconductor wafer comprising: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer; forming a protective layer on an upper face of the p-side nitride semiconductor layer in regions that include borders of areas to become the plurality of light emitting elements; reducing a resistance of the p-side nitride semiconductor in areas where no protective layer has been formed by annealing the semiconductor wafer; irradiating a laser beam on the substrate so as to form modified regions in the substrate; and obtaining a plurality of light emitting elements by dividing the semiconductor wafer in which the modified regions have been formed in the substrate.

Abstract: Various embodiments include methods and apparatuses, such as memory cells formed on two or more stacked decks. A method includes forming a first deck with first levels of conductor material and first levels of dielectric material over a substrate. Each level of the conductor material is separated from an adjacent level of conductor material by at least one of the first levels of dielectric material. A first opening is formed through the first levels of conductor material and dielectric material. A sacrificial material is formed at least partially filling the first opening. A second deck is formed over the first deck. The second deck has second levels of conductor material and second levels of dielectric material with each level of the conductor material being separated from an adjacent level of conductor material by at least one of the second levels of dielectric material. Additional apparatuses and methods are disclosed.

Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

Abstract: The present disclosure provides an array substrate and a display device. The array substrate includes a plurality of signal lines, a plurality of secondary discharging lines arranged substantially parallel to each other, each of the plurality secondary discharging being arranged to cross the plurality of signal lines, a plurality of first electrostatic discharging units arranged in one-to-one correspondence with the plurality of signal lines, and a primary discharging line connected to the plurality of secondary discharging lines. One end of each first electrostatic discharging unit is connected to its corresponding signal line, and the other end thereof is connected to one of the plurality of secondary discharging lines.

Abstract: A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a resist that is caused due to baking, UV curing, or other treatments in photolithography can be dispersed, contraction and deformation of the resist at an end of the second interconnect can be alleviated, and dimensions and shape of a interconnect, which is formed by etching, can be stabilized.

Abstract: A drift layer is made of a wide bandgap semiconductor. First well regions are formed on the drift layer. A source region is formed on each of the first well regions. A gate insulating film is formed on the first well regions. A first electrode is in contact with the source regions, and has diode characteristics allowing unipolar conduction to the drift layer between the first well regions. A second well region is formed on the drift layer. A second electrode is in contact with the second well region, and separated from a gate electrode and the first electrode.

Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.