Abstract: A slit is formed along a coupling portion at which a second interconnect is connected to a relatively large area interconnect or pad. Since tensile stress of a resist that is caused due to baking, UV curing, or other treatments in photolithography can be dispersed, contraction and deformation of the resist at an end of the second interconnect can be alleviated, and dimensions and shape of a interconnect, which is formed by etching, can be stabilized.

Abstract: A drift layer is made of a wide bandgap semiconductor. First well regions are formed on the drift layer. A source region is formed on each of the first well regions. A gate insulating film is formed on the first well regions. A first electrode is in contact with the source regions, and has diode characteristics allowing unipolar conduction to the drift layer between the first well regions. A second well region is formed on the drift layer. A second electrode is in contact with the second well region, and separated from a gate electrode and the first electrode.

Abstract: The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first active region and the second active region are disposed in the substrate. The gate structure includes a bottom, a first sidewall attached to the first active region, and a second sidewall attached to the second active region. The first sidewall and the bottom have a first point of intersection, and the first sidewall and a first horizontal line starting from the first point toward the substrate have a first included angle. The second sidewall and the bottom have a second point of intersection, and the second sidewall and a second horizontal line starting from the second point toward the substrate have a second included angle. The first included angle is different from the second included angle. A method for manufacturing a semiconductor device is provided herein.

Abstract: A chip includes a first group of dummy bumps disposed at a top surface of the chip in a first corner of the chip, a second group of dummy bumps disposed at the top surface of the chip in a second corner of the chip, and active bump connectors disposed at the top surface of the chip. The chip also includes an outer seal ring disposed around a periphery of the chip, a first seal ring arrangement disposed around the first group of dummy bumps, and a second seal ring arrangement disposed around the second group of dummy bumps. The first seal ring arrangement and second seal ring arrangement are disposed in dielectric layers underlying the first and second groups of dummy bumps.

Abstract: A quantum well device includes a first layer of a first two-dimensional material, a second layer of a second two-dimensional material, and a third layer of a third two-dimensional material disposed between the first layer and second layer. The first layer, the second layer, and the third layer are adhered predominantly by van der Waals force.

Abstract: A display apparatus includes a substrate having a display area in which an image is displayed and a peripheral area outside the display area; a thin film encapsulation layer at the display area, the thin film encapsulation layer including a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer that are stacked; a dam at the peripheral area; and an organic material detection part outside the dam, the organic material detection part including at least one detector. The first inorganic encapsulation layer and the second inorganic encapsulation layer extend from the display area to the peripheral area, and the first inorganic encapsulation layer has an opening that corresponds to at least a portion of the organic material detection part.

Abstract: A bi-directional semiconductor switching device includes first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.

Abstract: The disclosure relates to an electronic module and a manufacturing method of the same. The electronic module includes a substrate, an electronic component, a first package body, a magnetic layer, a coil and a second package body. The electronic component is on the substrate. The first package body is on the substrate and covers the electronic component. The magnetic layer is on the first package body. The coil is on the magnetic layer. The coil includes a first section and a second section spaced from the first section. The first section and the second section are connected by a conductive material. The second package body is on the magnetic layer and covers the coil.

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, source/drain regions on the fin, a recess between the source/drain regions, a device isolation region including a capping layer extending along an inner surface of the recess and a device isolating layer on the capping layer to fill the recess, a dummy gate structure on the device isolation region and including a dummy gate insulating layer, outer spacers on opposite sidewalls of the dummy gate structure, first inner spacers between the dummy gate structure and the outer spacers, and a second inner spacer between the device isolation region and the dummy gate insulating layer.

Abstract: A light emitting structure including mixing cups are described. In an embodiment, a light emitting structure includes a light emitting diode (LED) bonded to a substrate, a diffuser layer adjacent the LED, an angular filter directly over the diffuser layer and the LED, and an overcoat layer directly over the angular filter and the LED.

Abstract: A photodiode array includes a plurality of photodiodes formed in a semiconductor substrate. Each of the photodiodes includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, provided with respect to the first semiconductor region on one surface side of the semiconductor substrate, and having an impurity concentration higher than an impurity concentration of the first semiconductor region, a third semiconductor region of a second conductivity type, provided with respect to the first semiconductor region on the one surface side so as to surround the second semiconductor region separately from the second semiconductor region, and constituting a light detection region together with the first semiconductor region, and a through-electrode provided within a through-hole passing through the first semiconductor region and the second semiconductor region, and electrically connected to the third semiconductor region.

Abstract: Disclosed is a structure wherein lower source/drain regions of vertical field effect transistors (VFETs) of memory cells in a memory array are aligned above and electrically connected to buried bitlines. Each cell includes a VFET with a lower source/drain region, an upper source/drain region and at least one channel region extending vertically between the source/drain regions. The lower source/drain region is above and immediately adjacent to a buried bitline, which has the same or a narrower width than the lower source/drain region and which includes a pair of bitline sections and a semiconductor region positioned laterally between the sections. The semiconductor region is made of a different semiconductor material than the lower source/drain region. Also disclosed is a method that ensures that bitlines of a desired critical dimension can be achieved and that allows for size scaling of the memory array with minimal bitline coupling.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.

Abstract: A method of forming semiconductor nanorods includes: placing, in a chamber, a masking material and a base comprising a semiconductor, wherein an etching rate of the masking material in a chemical reaction with a reactant gas during dry etching is lower than an etching rate of a semiconductor in a chemical reaction with the reactant gas during dry etching; and performing dry-etching to form a plurality of dot-masks, each having a form of a dot containing the masking material, on a surface of the semiconductor and to remove a portion of the semiconductor exposed from the dot-masks, wherein the dry-etching is performed under a pressure in the chamber in a predetermined range that allows the masking material scattered by the etching to be adhered to a surface of the semiconductor with a predetermined size of the dots and a predetermined density of the dots.

Abstract: An organic EL display device has a semiconductor circuit substrate comprising a TFT and an organic passivation layer thereon. An AlO layer is formed over the organic passivation layer, and an electrode layer is formed on the AlO layer. The electrode layer connects with TFT via a through hole formed in the AlO layer and in the organic passivation layer.

Abstract: The method for manufacturing a plurality of optical modules each comprising a first (C1) and a second (C2) optical component comprises the steps of a) providing a first substrate wafer (S1) on which a plurality of the first optical components (C1) is present on a top side of the first substrate wafer; b) providing a second substrate wafer (S2) having a material region which is a continuous laterally defined region in which material of the second substrate is present, wherein a plurality of the second optical components (C2) is present in said material region; c) achieving a lateral alignment of the first (S1) and second (S2) substrate wafers such that each of the first optical components (C1) is present in a laterally defined region not overlapping said material region; d) interconnecting the first and second substrate wafers in said lateral alignment such that the top side of the first substrate wafer faces a bottom side of the second substrate wafer with no further wafer in between.

Abstract: A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed.

Abstract: The invention relates to an optoelectronic light-emitting device (1), including: at least one light-emitting diode (40) having an emitting surface (44) adapted to emit so-called excitation luminous radiation; and a photoluminescent material (31) that coats the emitting surface (44), the photoluminescent material containing photoluminescent particles adapted to convert said excitation luminous radiation through the emitting surface (44) at least in part into so-called photoluminescence luminous radiation. The optoelectronic device includes at least one photodiode (50) adjacent the light-emitting diode (40) having a receiving surface (54) coated by the photoluminescent material (31) and adapted to detect at least part of the excitation radiation and/or the photoluminescence radiation coming from the photoluminescent material (31) through the receiving surface.

Abstract: A semiconductor device includes: a semiconductor substrate; a gate electrode on the semiconductor substrate; a SiN film on the semiconductor substrate and the gate electrode; and an oxide film on the SiN film, wherein the oxide film is an atomic layer deposition film including atomic layers alternately deposited.

Abstract: A semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad.