Abstract: A light emitting diode has both end faces metallized and is mounted on a substrate with the light emitting junction perpendicular to the substrate. The electrically conductive ends are electrically bonded to conductive areas on the substrate by solder or conductive adhesive. LED dice can be placed on the substrate by temporarily attaching the dice to a tape which has been wrapped around a knife edge. The dice tilt as the tape wraps around the edge and are picked off one at a time by a vacuum collet while temporarily supported by a movable finger, and then transferred by the vacuum collet to a substrate. A similar method may be used for placing semiconductor dice on a substrate without the tilting of dice around the edge. In another embodiment, an array of LEDs can be assembled in windows through a metallized plastic tape which is bonded to a foundation with additional metallized leads.

Abstract: A lead frame for a semiconductor integrated circuit has a chip mounting section for carrying a semiconductor chip and a peripheral section where a plurality of outer leads are juxtaposed with each other. The semiconductor chip will be sealed by a sealing resin when mounted on said chip mounting section. The outer leads extend outwardly from the chip mounting section and are adapted to electrically connected with the semiconductor ship mounted. Each outer lead has a first offset portion which is spaced more from a first adjacent outer lead on one side thereof than from a second adjacent outer lead on the other side thereof and a second offset portion which is spaced more from the second adjacent outer lead than from the first adjacent outer lead. The first and second offset portions of each outer lead is arranged in a staggered pattern.

Abstract: A large area photovoltaic device includes a plurality of photovoltaic regions electrically interconnected in parallel. The regions are defined by through hole connections which establish electrical contact between a top transparent electrode and a monolithic metal substrate. A second terminal is provided by a bottom, metallic electrode disposed upon an electrically insulating layer supported on the metallic substrate.

Abstract: A novel electrically programmable and erasable memory cell, comprising a single transistor, which is a floating gate transistor and has no selection transistor. Means are provided for establishing a high capacitive coupling between the drain and the floating gate. The capacitive coupling between the source and the floating gate is low, as is normally the case. Preferably, the control gate only partly covers the floating gate. Another part of the floating gate is covered by a semiconductor layer connected to the drain. It is the latter layer which establishes the high capacitive coupling according to the invention. Programming can then take place by the Fowler-Nordheim effect with the source under high impedance, i.e. without hot electron effect.

Abstract: A diffused layer serves as a source and a drain. It is formed comprised of a deep first diffused layer and a shallow second diffused layer positioned between the first diffused layer and the channel region. In the second diffused region, a distribution in a depth direction of carriers has a profile in which the concentration is more than 5.times.10.sup.18 cm.sup.-3 at the peak and is in correspondence with a carrier concentration of the semiconductor substrate at a depth less than 0.04 .mu.m. Since the second diffused layer has a high concentration, the short-channel effect can be suppressed. As the second diffused region, a solid phase diffusion source such as an impurity doped silicate glass is used.

Abstract: A compliant integrated circuit (IC) wiring substrate (10) has an insulative carrier film (14) and a plurality of micro-beam conductors (12) in the carrier film. Each of the plurality of micro-beam conductors has a pair of contact bumps (16 and 18) connected to respective posts (22 and 24). A beam element (20) connects the pair of contact bumps and posts at opposing ends and opposing surfaces of the beam element. The plurality of micro-beam conductors extend through the thickness of the carrier film such that the pair of contact bumps protrude from the opposite surfaces of the carrier film. The compliance of the wiring substrate can be varied by varying locations of apertures in the insulative carrier film.

Abstract: Disclosed is a method of forming an interconnection pattern which causes no disconnection even when making contact with water in the atmosphere. An interconnection layer is formed on a semiconductor substrate. The interconnection layer is selectively etched by employing a halogen-type gas, to form an interconnection pattern. Ultraviolet rays are directed onto the interconnection pattern in the atmosphere including a hydrogen gas. This method avoids generation of hydrogen halogenide which causes corrosion of metal interconnections even when the metal interconnections make contact with water in the atmosphere, thereby to prevent disconnections of the metal interconnections.

Abstract: A silicon-on-insulator (SOI) substrate has an insulating substrate having a glass substrate and an insulating layer formed on the substrate, an array of isolated silicon film pieces formed on a pixel area of the insulating substrate, a meshed silicon film formed on a drive circuit area of the insulating substrate, both the meshed and isolated silicon films being composed of hydrogenated amorphous silicon or polycrystalline silicon. In manufacturing a semiconductor device from the SOI substrate, the meshed silicon film is annealed for recrystallizing selectively from the isolated silicon film pieces by induction heating. A reliable and reproducible semiconductor device for use in LCD is fabricated at a low cost.

Abstract: A radiation detector includes a photovoltaic diode mesa structure (16) having of a plurality of sub-mesa structures (16a, 16b). Each of said sub-mesa structures includes a first layer (14a) of semiconductor material having a first type of electrical conductivity and a second layer (14b) having a second type of electrical conductivity such that a p-n junction is formed between the first and the second layers. Metalization (24) is disposed within a trench (30a) that runs between the sub-mesas and includes a tab portion (24a) that extends upwardly over a sidewall of each of said sub-mesa structures so as to electrically contact the second layer contained within each. As a result, each of said sub-mesa structures are electrically connected in parallel.

Abstract: An opto-electronic component comprises a substrate of InP (4, 5) with stacks of quantum wells (6) grown on both surfaces of the substrate. Layers (7) of n doped InP having p-doped regions (8) are formed on the outer surface of the quantum well structures. In use, voltages V1 and V2 may be applied to electrodes (1) enabling the component to be used for a number of applications, e.g. as a detector/modulator pair, in close coupled arrays of modulators, etc.

Abstract: A gallium arsenide Monolithic-Microwave-Integrated-Circuit (MMIC) flip chip or other microelectronic circuit structure (10) includes a plated gold bridge (28) which serves as metal interconnect crossover between sites (24,-26) on a substrate (12). A first inorganic dielectric passivation layer (16), preferably of silicon dioxide, is formed under and supports the bridge (28). A second inorganic dielectric passivation layer (30), also preferably of silicon dioxide, is formed over and encapsulates the bridge (28) and the chip surface. A titanium/gold/titanium membrane (22) is formed under the bridge (28) to enable adhesion of the bridge (28) to the first passivation layer (16) and form plating contacts for the bridge (28). A contact bump post (38) is formed in a bump hole or via (32) which extends through the first and second passivation layers (16,30) to a bump contact site (34) on the substrate (12).

Abstract: A method and the resulting product for isolating lightly doped silicon islands from each other and from a common substrate. The substrate is covered with a first heavily doped epi layer. The first layer is covered with a lightly doped second epi layer. A pair of spaced deep trenches are provided which extend from the top surface of the second layer, through the first layer and into the substrate. The interior walls of the trenches are lined with oxide. A pair of heavily doped reach-through diffusions extending from said top surface to the first layer is oriented perpendicularly to the deep trenches and fully extends between the trenches. The heavily doped reach-through diffusions and the contiguous first layer are removed by a single anisotropic etching step to yield silicon islands isolated by air except where the islands contact the oxide-lined deep trenches. The air isolation preferably is partially replaced with other dielectric material.

Abstract: The invention relates to an opto-electronic component having a narrow aperture angle. The conventional design of components transmitting radiation or reacting to radiation and concentrating that radiation with the aid of lenses results, on account of the increasing distance between the lens and the semiconductor chip, in increasing component dimensions in the radiating or detecting direction with an increasingly narrow aperture angle. In accordance with the invention, a parabolic or approximately parabolic reflector is provided that is connected to a support strip supporting the semiconductor chip such that the latter is as close as possible to the focal point of the parabolic or approximately parabolic surface of the reflector. The reflector is preferably connected to the support strip by engaging elements and surrounded by a housing.

Abstract: A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices.

Abstract: A self clamping heat sink for releasable connection to an electrical component having a bottom surface and a top surface. The self clamping heat sink includes a base and a pair of inverted U-shaped spring arms at opposite sides of the base which extend upwardly from the base. A clamping finger extends inwardly from the outer leg portion of each spring arm to a free end which overlies the base. The free ends of the spring arms are raised to an upper position relative the base by applying external force to squeeze the outer leg portions of the spring arm toward each other. This enables an electrical component to be placed on the base and below the free ends of the clamping fingers. When external force is removed from the spring arms, the clamping fingers try to return to their normal lower position and engage the top surface of the electrical component so that the electrical component is clamped between the base and the fingers.

Abstract: A thin-film arrangement for a non-planar structure is described. The structure includes a substrate and a plurality of thin-film layers stacked on top of each other above the substrate. The layers contain conductive patterns and vias that provide connections between the conductive pattern in one of the layers to the conductive pattern in another layer. Vias that provide a connection between the conductive pattern of one layer to the conductive pattern in another remotely located layer are offset and in contact with respect to each other and are positioned in a non-linear arrangement, preferably in the form of a helix or a multiple helix.

Abstract: A semiconductor light-emitting device includes a plurality of light-emitting elements disposed on a single substrate. Each light-emitting element includes a plurality of light-emitting regions that can be driven independent of each other to emit light. The largest spacing between light-emitting regions of each light-emitting element is selected such that light emitted from any of the light-emitting regions of that element can impinge on the same light-responsive element associated with that light-emitting element.

Abstract: The invention provides a compound semiconductor multilayer structure having a two-dimensional electron gas, which is applicable to field effect transistors. A ternary compound InGaAs planar channel layer serving as a quantum well has a variation of an In (indium) fraction in a perpendicular direction to a heterojunction interface. The variation has a step-graded profile with taking a maximum value at or in the vicinity of a portion where the two-dimensional electron gas takes a maximum density. Such quantum well has most large depth at a portion except for adjacent portions to the heterojunction interfaces. Such multilayer structure provides a great electron mobility and a strong electron confinement to major electrons at a high electron density portion.

Abstract: A voltage controlled thyristor includes an intrinsic layer of material between an anode and a cathode and a gate region between the intrinsic layer and the cathode comprising a lightly doped P type layer with more heavily doped P type regions extending through the lightly doped layer into the intrinsic layer. The more heavily doped P type regions are interspersed among shallower N doped regions of the cathode. In a preferred embodiment, interdigitated ohmic contacts are formed on one surface to the N doped cathode regions and the P doped regions of the control gate. In a preferred embodiment, the anode and cathode emitters have a porous construction in which a lightly doped layer or region has a more heavily doped region or regions therein.

Abstract: This invention embodies single mirror light-emitting diodes (LEDs) with enhanced intensity. The LEDs are Group III-V and/or II-IV compound semiconductor structures with a single metallic mirror. The enhanced intensity is obtained by placing an active region of the LED having from two to ten, preferably from four to eight, quantum wells at an anti-node of the optical node of the device created by a nearby metallic mirror. Such multiquantum well LED structures exhibit enhanced efficiencies approaching that of a perfect isotropic emitter.