Abstract: A first metallization layer is locally formed on the surface of a semiconductor substrate thereby leaving portions of the semiconductor substrate's surface exposed. A first silicon oxide layer is then formed in such a manner that it covers the exposed portions of the semiconductor substrate's surface and the first metallization layer. This is followed by the formation of an HMDS molecular layer on the first silicon oxide layer. Then, a second silicon oxide is formed on the molecular layer by means of a CVD process utilizing the chemical reaction of ozone with TEOS. Finally, a second metallization layer is locally formed on the second silicon oxide layer.

Abstract: In a semiconductor pressure sensor reducing the stress applied by a thick film substrate and preventing the rising of a die bonding material, a sensor chip having a thin wall diaphragm is fixed to a thick film substrate by a die bonding material, such as silicone resin. A convex member of a glass material is interposed between the thick film substrate and the sensor chip and fixed by the die bonding material. With this arrangement, unintended deformation of the diaphragm of the sensor chip can be prevented and a highly accurate, less expensive semiconductor pressure sensor can be provided.

Abstract: A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N-LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.

Abstract: A resin-sealed type semiconductor device is provided which has a lead array with a plurality of leads arranged at a predetermined interval. A first die pad is provided substantially flush with the lead array. A semiconductor chip is mounted on the first pad and electrically connected to the lead array. A second die pad is arranged in a separate, side-by-side relation to the first die pad. The portion of the lead array, first die pad with the semiconductor chip mounted thereon and second die pad are covered with a resin molding body as an integral unit.

Abstract: A semiconductor light emitting element comprising an n-type semiconductor substrate and a light emitting part comprising an n-type cladding layer composed of an InGaAlP compound semiconductor material, an active layer and a p-type cladding layer formed in that order from the substrate side by double heterojunction, wherein said semiconductor light emitting element satisfies at least one of the following conditions:A. the thickness of said active layer being greater than 0.75 .mu.m and not more than 1.5 .mu.m, andB. the thickness of said p-type cladding layer being 0.5 .mu.m-2.0 .mu.m. According to the light emitting element of the present invention, an overflow of electron into the p-type cladding layer can be suppressed by setting the thickness of the active layer and the p-type cladding layer to fall within the above-mentioned specific ranges, as a result of which the element shows luminous efficiency peaked within the specified range.

Abstract: In a space surrounded by outer frames formed in the shape of as rectangle is disposed a die pad in the shape of a square for mounting a semiconductor chip having electrodes. Each of the outer frames is connected with a plurality of outer leads respectively continuous with inner leads which are used for electrical connection and extended toward the die pad. Each inner lead is extended to the vicinity of a position where each electrode of the semiconductor chip is to be formed. The corners of the die pad are respectively provided with support members extending to positions away from a dam bar by a predetermined distance. The support members are connected with the inner leads via a square ring-shaped insulating member. Thus, the die pad is supported by the outer frames via the support members. Since there is no need to provide a die pad lead, the space at the corner conventionally occupied by the die pad lead can be utilized for wiring, and the leads can be easily led in.

Abstract: An integrated circuit capacitor (20) includes a bottom electrode structure (24) having an adhesion metal portion (34), a noble metal portion (36), and a second noble metal layer (40). A process of manufacture includes annealing the adhesion metal portion (34) and the noble metal portion (36) prior to the deposition of second noble metal layer (40) for purposes of forming barrier region (38). The electrode (24) preferably contacts metal oxide layer (26), which is made of a perovskite or perovskite-like layered superlattice material. A temporary capping layer (59) is formed and removed in manufacture, which serves to increase polarization potential from the device by at least 40%.

Abstract: An integrated circuit package for housing an integrated circuit (IC) chip and providing electrical connectivity of data signals and voltage signals between the IC chip and an electronic component includes a substrate, an IC chip affixed to the substrate and at least three conductive layers on the substrate. The three conductive layers include at least a first voltage layer adjacent to the substrate for providing a first reference voltage signal (i.e., ground) to the IC chip, a second voltage layer for providing a second reference voltage signal (i.e., power) to the IC chip, and a signal layer. To maximize speed and minimize complexing all of the data signals to the IC chip are routed on the signal layer. The power and ground layers are closely coupled and separated by a dielectric layer having a relatively high dielectric constant for providing significant decoupling capacitance. A low dielectric layer is provided for separating the power layer from the signal layer.

Abstract: A MOS type semiconductor device has a gate whose length is 170 nm (0.17 .mu.m) or less, a junction depth of source and drain diffusion layers in the vicinity of a channel is 22 nm or less, and a concentration of impurities at the surface in the source and drain diffusion layers is made to 10.sup.20 cm.sup.-3 or more. Such structure is obtained using solid phase diffusion using heat range from 950.degree. C. to 1050.degree. C. and/or narrowing gate width by ashing or etching. The other MOS type semiconductor device is characterized in that the relationship between the junction depth x.sub.j ?nm! in the source and drain diffusion layer regions and the effective channel length L.sub.eff ?nm! is determined by L.sub.eff >0.69 x.sub.j -6.17.

Abstract: In a semiconductor device including a plurality of semiconductor cells each of which has a diffusion area, a first metal layer, and a connecting portion, the first metal layer overlies whole of the diffusion area while the connecting portion covers almost whole of the diffusion area. The semiconductor device further includes a second metal layer, and first and second power supply lines. The second metal layer has an interconnecting area positioned above the semiconductor cells and an overlapping area overlapping on the first metal layer. Each of the first and the second power supply lines consists of the overlapping area. The semiconductor cells are electrically connected to each other by a third metal layer and the interconnecting area of the second metal layer.

Abstract: A gate array base cell is disclosed which provides decreased input loading. The preferred base cell comprises two rows of CMOS sites. Each row comprises small CMOS sites CS and large CMOS sites CL. The transistor gates in the small CMOS site CS are narrower than the transistor gates in the large CMOS site CL. Preferably, the CS sites comprise transistor gates one half the size of transistor gates in the CL sites so that transistor the CS sites may be connected in parallel to form the electrical equivalent of transistor gates in the CL sites.

Abstract: An IC carrier for electric testing of an IC package enables an IC package to be loaded on or unloaded from it smoothly without bending any of closely arranged fine leads, and prevents the leads from being deformed by falling impact when it is dropped. The IC carrier for an IC package, having an array of leads, comprises an array of sockets for mating with the array of leads, wherein selected one of the sockets differs in clearance between a width of each of the sockets and a width of each of the leads to be mated from the other ones in a cross section of an array. For instance, an array of sockets having holes to mate with leads having a single diameter of an IC package are arranged so that inner diameters of the holes in an outer part of the array is larger than those in a central part of the array. The technique is applicable to both a flat IC package (QFP or SOP) and a pin grid array IC package (PGA).

Abstract: An intermetallic compound semiconductor thin film comprises thin film made of either InSb or GaAs heterostructure on a silicon substrate. Preferably, the thin film is grown by a Molecular Beam Epitaxy method.

Abstract: A new method of fabricating a polycide gate is described. A gate polysilicon layer is provided a gate oxide layer on the surface of a substrate. A thin conducting diffusion barrier is deposited overlying the gate polysilicon layer. A of tungsten silicide is deposited overlying the thin diffusion barrier layer wherein a reaction gas in the deposition contains fluorine atoms and wherein fluorine atoms are incorporated into the tungsten layer. The gate polysilicon, thin conducting barrier, and tungsten silicide layers are patterned form the polycide gate structures. The wafer is annealed complete formation of the polycide gate structures wherein number of fluorine atoms from the tungsten silicide layer into the gate polysilicon layer are minimized by presence of the thin conducting diffusion barrier layer wherein because the diffusion of the fluorine atoms is the thickness of the gate oxide layer does not This prevents the device from degradation such as voltage shift and saturation current descrease.

Abstract: A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.

Abstract: Two modules, each of which has a plurality of memory IC chips installed therein, are stacked to form a module unit. Furthermore, a plurality of the module units are installed on a mother board so as to form a multilevel semiconductor integrated circuit device. By further stacking a specific module containing an IC chip for replacing the functions of a defective chip, a repair process can be conducted more easily and efficiently. Alternatively, instead of the module units, a plurality of TAB packages stacked in a multilayer structure are installed on the mother board. Outer leads of each of the TAB packages and terminal pads on the circuit board are respectively connected to each other in a one-to-one way. Thus, only a defective TAB package need be taken away and consequently, efficiency in the repair process further improves.

Abstract: A quantum well intersubband infrared (IR) photodetector has a spectral response tunable by an external voltage. The photodetector consists of multiple doped quantum wells with different well widths and barrier heights. The preferred embodiment is made by repeating the whole structure of the active region of a multiple quantum well intersubband IR photodetector. Differences between repeats or groups of well widths and barrier heights result in differences in the spectral IR response of the different repeats. The device resistance of a given group is designed to be very different from those for all the other groups. As a function of an applied voltage, the repeat with the highest resistance will be turned on to detect IR with the response peak at a wavelength .lambda..sub.1. Subsequently, the next highest resistance repeat will turn on when increasing voltage with its response peaked at .lambda..sub.2, and so on. Since .lambda..sub.1, .lambda..sub.

Abstract: A CVD process for producing a rare earth-doped, epitaxial semiconductor layer on a substrate is disclosed. The process utilizes a silane or germane and a rare earth compound in the gas phase. By this method single phase, rare earth-doped semiconductor layers, supersaturated in the rare earth, are produced. The preferred rare earth is erbium and the preferred precursors for depositing erbium by CVD are erbium hexafluoroacetylacetonate, acetylacetonate, tetramethylheptanedionate and flurooctanedionate. The process may be used to produce optoelectronic devices comprising a silicon substrate and an erbium-doped epitaxial silicon film.

Abstract: A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference.

Abstract: A high voltage silicon rectifier includes a substrate portion and an epitaxial mesa portion that is a frustrum of a pyramid with a substantially square cross section and side walls that make a forty five degree angle with the substrate portion. The mesa portion includes three germanium doped layers that introduce strain to speed up recombination of charge carriers.