Abstract: A photocoupler device includes a light-emitting chip, a light-receiving chip, a light-emitting side lead frame for individually holding the light emitting chip and a light-receiving side lead frame for individually holding the light-receiving chip. The light-emitting and light-receiving chips are opposed to each other so as to be optically coupled and covered with a light-transmissive resin as a first molding layer, in the whole part except in the outside connecting terminal portions of the two lead frames. The first molding layer is further covered with an opaque resin as a second molding layer. In such a photocoupler device, the light-transmissive resin is made to contain fillers in an amount of 80% by weight or more and directly cover the light-emitting chip, without needing silicone-resin coating for protecting the light-emitting chip.

Abstract: A semiconductor device having a semiconductor element mounted on an insulating substrate and a decoupling capacitor provided on the semiconductor element. The semiconductor device minimizes the occurrence of switching noise. The semiconductor device comprises an insulating substrate, a semiconductor element mounted on said insulating substrate, and a decoupling capacitor which is joined to the upper surface of said semiconductor element and is electrically connected to said semiconductor element, wherein said decoupling capacitor has a coefficient of thermal expansion close to the coefficient of thermal expansion of said semiconductor element, and is electrically connected to said semiconductor element by soldering and is further secured to said semiconductor element.

Abstract: A semiconductor memory device in which word lines are arranged so as to improve the yield with respect to bridging defects. The semiconductor memory device of the present invention has a plurality of interconnects arranged in parallel on a cell array portion, in which the interconnects are comprised of power lines and ground lines arranged alternately on the cell array portion, main word lines arranged on each side of the power lines, and a plurality of block word lines sequentially arranged between a single main word line and a ground line adjacent thereto and controlled by the main word line. In this way, interconnects are arranged in alternating groups so that interconnects having the same logic level during the standby mode are grouped together. The result of this arrangement is that interconnect bridges within a group will not lead to increased standby current, thereby substantially improving the yield of the semiconductor memory device.

Abstract: A mid-infrared emitting diode with a substrate which is transparent to radiation produced by the device by virtue of the Moss-Burstein shift which is induced in the substrate by heavy doping. Emission from the device takes place via said substrate with a significant increase in external efficiency due to avoidance of obscuration by metallic contact.

Abstract: A container has an upper opening, a plurality of semiconductor elements and electrode terminals connected to the semiconductor elements. A cover member closing the opening has insertion holes formed therethrough from its lower surface to its upper surface. The cover member is coupled with the container by inserting the electrode terminals through the insertion holes to make them vertically project from the upper surface, and bending the projecting electrode terminals. The cover member has projections provided adjacent to the insertion holes. Each of the vertically projecting electrode terminals is bent through more than 90.degree. over a corresponding one of the projections, with its bent corner portion supported on the edge of the projection, and arranged parallel to the upper surface of the cover member as a result of a spring back effect.

Abstract: The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the device's performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.

Abstract: A charge storage device, such as an integrated circuit memory, including a dielectric comprising a barium-strontium-niobium oxide. A liquid precursor including the metals barium, strontium, and niobium is prepared and applied to a platinum electrode. The precursor is baked and annealed to form a dielectric having the formula Ba.sub.x Sr.sub.y Nb.sub.z O.sub.30, where x=1.3 to 3.5, y=1.5 to 3.7, and z=10. A top platinum electrode is then formed to provide a memory cell capacitor. Optimum results to date have been obtained with Ba.sub.2 Sr.sub.3 Nb.sub.10 O.sub.30, which yields a memory cell dielectric with dielectric constant over 1000 and a leakage current of less than 10.sup.-5 amperes per square centimeter for voltages up to 5 volts.

Abstract: A bipolar transistor, an nMOS transistor and pMOS transistor are formed at a main surface of a p-type semiconductor substrate. The bipolar transistor includes a collector layer, a base layer and an emitter layer. Collector layer located immediately under base layer contains impurity of n-type at a concentration not more than 5xl0.sup.18 cm.sup.-3. Base layer located immediately under emitter layer has a diffusion depth not more than 0.3 .mu.m. A semiconductor device including the bipolar transistor having the above structure is used in a circuit performing small amplitude operation. Thereby, it is possible to provide the semiconductor device having the bipolar transistor, which can be manufactured at a low cost and can operate at a high speed.

Abstract: Main current terminals (31, 32) electrically coupled to main electrodes of IGBT elements (27) which are loaded on a power substrate (30) project from a side wall of a case (21) to the exterior. The main current terminals (31, 32), which are in the form of flat plates having the same plane contours in principal parts thereof, are arranged to be parallel to each other and overlap with each other. Thus, inductances of the main current terminals (31, 32) are suppressed. An insulating member (33) is interposed between the portions of the main current terminals (31, 32) outwardly projecting from the case (21), while outwardly extending from the plane contours of the main current terminals (31, 32). Therefore, a withstand voltage across these portions of the main current terminals (31, 32) is maintained at a high value.

Abstract: Insulating trenches (2) in the silicon layer of an SOI substrate that extend onto the insulating layer of the SOI substrate define silicon islands (3). At least one of the silicon islands (3) is an interconnect segment (3a) by a diffusion zone that is arranged at the walls of the surrounding trench (2) and that is formed by drive-out from an occupation layer introduced into the trench. The interconnect segment (3a) is suitable as an underpass for crossing interconnects (6a,6b) or as an additional metallization level.

Abstract: An integrated circuit and a process for manufacturing the same wherein the integrated circuit includes a substrate, a first insulative layer disposed on the substrate, and a first conductive layer disposed on the first insulative layer, the first conductive layer having a plurality of conductive channels arranged into horizontal tracks. The plurality of conductive channels are for providing two power sources V.sub.SS and V.sub.CC to cells (e.g. standard cells in control blocks) in the integrated circuit. A second insulative layer is disposed on the first conductive layer, and a second conductive layer is disposed on the second insulative layer, the second conductive layer arranged into a plurality of vertical tracks, each of the plurality of vertical tracks are broken into a plurality of segments. Each of the plurality of segments are for carrying one of the power sources, V.sub.SS and V.sub.

Abstract: A variable-width lead interconnection structure disposed between a printed circuit board and a multichip module is presented. An edge clip with leads having a widened middle section is provided to optimize manufacturability and electrical performance. Each lead has a characteristic width and spacing of conventional leads where the leads are soldered to a multichip module or PCB. However, in between each end, each lead has a middle section that is widened to provide a characteristic impedance closer to the ideal 50 ohms, thus producing structures with better return loss at high frequencies.

Abstract: A test fixture for testing an integrated circuit having leads. The test fixture includes a substrate with top and bottom surfaces and holes extending from the top to the bottom surface. The integrated circuit is mounted on the top surface with each lead located above each hole. Contact flippers are located on the top surface of the substrate, with the contact flippers extending between the leads and the holes. Shuttle springs are located along the bottom surface and extend across the holes. Shuttles are inserted into each hole so that upon contact by the leads against the contact flippers, the shuttles move downward and against the upward pressure from the shuttle springs to provide a resilient connection between the test fixture and the integrated circuit.

Abstract: A low profile semiconductor device (24) is manufactured by mounting a semiconductor die (26) onto a substrate (28) using an interposer (30). The interposer couples an active surface (32) of the die (26) to conductive traces (33) on the top surface of the substrate. The interposer is directionally conductive so that electrical conductivity is limited to the z-direction through thickness of the interposer. The interposer both affixes the die to the substrate and provides the first level of interconnects for the device. The inactive surface (36) of the die can be exposed for efficient thermal dissipation. An optional heat spreader (50) may be added for increased thermal management. The device may be overmolded, glob-topped, capped, or unencapsulated. Separate die-attach and wire bonding processes are eliminated. A second level of interconnects are provided by either solder balls (38), solder columns (44), or pins (64).

Abstract: Diffusion of ion-implanted dopant is controlled by incorporating electrically inactive impurity in a semiconductor layer by at least one crystal growth technique.

Abstract: A method for fabricating an integrated circuit transistor begins with forming a gate electrode over an insulating layer grown on a conductive layer. Sidewall spacers are formed alongside vertical edges of the gate electrode and a mask is applied to a drain region. A relatively fast-diffusing dopant is then implanted into a source region in the conductive layer. Thereafter, the mask is removed and the drain region is implanted with a relatively slow-diffusing dopant. Finally, the conductive layer is annealed, causing the relatively fast-diffusing dopant to diffuse beneath the source sidewall spacer to a location approximately beneath the vertical edge of the source side of the gate electrode, and causing the relatively slow-diffusing dopant to extend beneath the drain sidewall spacer a lesser distance, so that the drain junction is laterally spaced from underneath the gate electrode.

Abstract: N-type doping in III-V-nitride semiconductor compounds, i.e. GaN-based compounds such as GaN, AlGaN, AlInN, InGaN, or AlGaInN, can be optimized to improve N-contact electrical resistance, carrier injection, forward voltage, and recombination characteristics without inducing cracking of the device layers. The N-type layer is constructed of sub-layers such that an N-type sub-layer is provided for each desired characteristic or property. The thickness of each sub-layer is carefully selected to avoid material cracking: the higher the required doping, the smaller the corresponding thickness. In illustration, the buffer layer of a light emitting device (LED) has three sub-layers. The first sub-layer is lightly doped to avoid cracking and is grown to the desired thickness for good material quality. The second sub-layer is heavily doped to provide good N-contact and electrical resistivity characteristics and is kept correspondingly as thin as necessary to avoid material cracking.

Abstract: A process for fabricating CMOS devices has been developed, in which decreased cycle time has been achieved, via a reduction in photomasking steps. The low cycle time CMOS process features the use of only one photo mask to create both the lightly doped, as well as the heavily doped N type, source and drain regions, by performing both implantations, after creation of the insulator sidewall spacer. In addition the P type source and drain regions are formed, using an oxide layer as a blockout for the P well region, thus eliminating the use of another photomasking procedure.

Abstract: A contact structure includes a depression formed in an insulation layer covered by an etching resistant layer and a through hole provided in the depression, wherein a ring-shaped wall member is provided on the depression such that the space formed inside the ring-shaped wall member continues to the through hole. The ring-shaped wall member is formed of a material having an etching rate different from the material forming insulation layer or the etching resistant layer.

Abstract: A process for fabricating both CMOS and LDMOS transistors includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming MOSFET body regions. Similarly, a process for fabricating both CMOS and NPN transistors includes a high temperature, long diffusion subsequent to deposition of the polysilicon gate for forming NPN base regions. In both processes, the threshold voltage of the PMOS devices is adjusted subsequent to both gate formation and the high temperature, long diffusions by implanting a suitable dopant into the PMOS channel through the gate. Since the gate is formed prior to threshold adjust, high temperature processing and long diffusions requiring the presence of the gate are completed without adversely affecting the adjusted threshold voltage. The p+ source/drain implant mask can be used to restrict the threshold adjust implant to the PMOS devices, thereby avoiding adversely affecting other devices in the integrated circuit.