Abstract: A semiconductor device having shallow junction, in which carrier concentration will not be reduced, sheet resistance will not be increased, and contact characteristic at a surface will not become inferior, is provided. A gate electrode is provided on a semiconductor substrate. At a surface of semiconductor substrate, a pair of source/drain layers having top and bottom surfaces are provided on both sides of gate electrode. In source/drain layer, a secondary-defect layer which extends horizontally is formed between top surface and bottom surface.

Abstract: In the light emitting element comprising an n-type semiconductor substrate, a lower electrode formed on the lower surface of the substrate, and a light emitting part having a pn junction, which is composed of an InGaAlP compound semiconductor material, a p-type current diffusing layer and an upper electrode which are laminated on the upper surface of the substrate in that order from the substrate side, the improvement wherein a carrier concentration of the current diffusing layer is lower on a light emitting part side thereof than that on an upper electrode side thereof, and at least the upper electrode side of the current diffusing layer is composed of GaP. By employing such structure, diffusion of the dopant to a light emitting part can be suppressed even when the carrier concentration of the upper part of the current diffusing layer is set to be higher, thereby affording a lower resistance of the current diffusing layer as a whole.

Abstract: In a complementary MIS semiconductor device of a dual gate structure, an N-type polysilicon layer for an N-channel transistor and a P-type polysilicon layer for a P-channel transistor are formed on a gate oxide film and a field oxide film. A recessed portion is formed on the field oxide film in a region including a junctioning region of the N-type polysilicon layer and the P-type polysilicon layer such that thicknesses of the polysilicon layers are reduced. A continuous silicide layer is formed on the polysilicon layers. The silicide layer is thin in the recessed portion on the field oxide film and is thick on an active region of each of the transistors. In this semiconductor device of a dual gate type, it is possible to prevent impurities of the polysilicon layers of gate electrodes from being diffused in a transversal direction and restrain an increase in resistance value of each of the gate electrodes.

Abstract: An optoelectronic device based on a conduction constriction through which charge carriers pass ballistically. The constriction has a cross-sectional area of 2 square microns or less and a thickness D and is made of doped semiconductor material with a carrier mobility .mu.. The thickness D is selected to be near to a characteristic path length D.sub.mes defined by D.sup.2.sub.mes =(h/2e)*.mu. where h is Planck's constant and e the elementary charge. The device can be used as a heterodyne radiation detector for detecting radiation in the frequency range between 3 GHz and 3 THz and is capable of detecting signals with a power of less than 10.sup.-14 watts in room temperature operation. The device can also be operated as the front end of a spectrometer. Other applications of the device include use as a high frequency AC current source or oscillator for microelectronics, for instance in the 100 to 500 GHz range.

Abstract: An integrated circuit (10), which is designed using standard cells (20, 22, 24, 26, 28, 30, 32, 34, 35, 36, 37, 28, 40, 42, 44, 46, 48, 50, 52), usually has one or more empty spaces (54) wherein no circuitry is formed. These empty spaces may be used to form capacitor standard cells which have capacitors (see FIGS. 3 and 4) to both ground and power supply lines within the integrated circuit. These capacitors are used to reduce noise in the power and supply lines in a manner more useful/efficient than known methods. The capacitor standard cell taught herein is more useful/efficient due to the fact that the capacitance provided by these standard cells is distributed over the entire integrated circuit in small portions (i.e., standard cells are placed all over the integrated circuit (10)), and is placed close to the logic which is switching. It is the switching logic which is the root of a large portion of internal integrated circuit noise.

Abstract: A semiconductor device is provided with an organic material which is formed by a solid-state mixture of organic donor and organic acceptor molecules. A semiconducting solid-state mixture is known with molar ratios between donor and acceptor molecules of 1.3:2 and 1.66:2. The known solid-state mixture has the disadvantage that its electrical conductivity is comparatively high, so that it is not possible to manufacture switchable devices from the mixture. Here the material includes an n- or p-type semiconductor material, the n-type semiconductor material having a molar ratio between the donor and acceptor molecules below 0.05, and the p-type semiconductor material having this ratio above 20. These solid-state mixtures may be used for manufacturing switchable semiconductor devices. The n- and p-type organic solid-state mixtures can be used for manufacturing transistors, diodes, and field effect transistors in a same manner as, for example, doped silicon or germanium.

Abstract: The invention provides light sources which are easily compatible with standard silicon VLSI processing and can be located directly in the material of the silicon VLSI chip. P-type silicon substrate is processed to produce proturbances, the proturbances preferably having tip dimensions on the order of 5-10 mm. A native oxide film (SiO.sub.2) is caused to develop on the surface of the silicon substrate. A thin, transparent, conductive film is then deposited on top of the SiO.sub.2. Electrical contacts are made to the top of the conductive film and to the bottom of the silicon substrate. The carriers for electroluminescence are supplied by the P-doped silicon substrate (holes) and the conductive film (electrons). When a voltage is applied across the layers via the electrical contacts, the holes are concentrated in the region of the tip of the proturbances because the electric field lines concentrate near a pointed object, and electron current across the SiO.sub.

Abstract: Semiconductor light emitting and sensing devices are comprised of a lattice matching wurtzite structure oxide substrate and a III-V nitride compound semiconductor single crystal film epitaxially grown on the substrate. Single crystals of these oxides are grown and the substrates are produced. The lattice matching substrates include Lithium Aluminum Oxide (LiAlO.sub.2), Lithium Gallium Oxide (LiGaO.sub.2), Lithium Silicon Oxide (Li.sub.2 SiO.sub.3), Lithium Germanium Oxide (Li.sub.2 GeO.sub.3), Sodium Aluminum Oxide (NaAlO.sub.2), Sodium Gallium Oxide (NaGaO.sub.2), Sodium Germanium Oxide (Na.sub.2 GeO.sub.3), Sodium Silicon Oxide (Na.sub.2 SiO.sub.3), Lithium Phosphor Oxide (Li.sub.3 PO.sub.4), Lithium Arsenic Oxide (Li.sub.3 AsO.sub.4), Lithium Vanadium Oxide (Li.sub.3 VO.sub.4), Lithium Magnesium Germanium Oxide (Li.sub.2 MgGeO.sub.4), Lithium Zinc Germanium Oxide (Li.sub.2 ZnGeO.sub.4), Lithium Cadmium Germanium Oxide (Li.sub.2 CdGeO.sub.4), Lithium Magnesium Silicon Oxide (Li.sub.2 MgSiO.sub.

Abstract: On a semiconductor substrate, a floating gate electrode composed of a first layer of polysilicon is disposed through a gate dielectric film, and the drain diffusion layer contacts with the floating gate electrode by self-alignment.. The source diffusion layer is disposed to have an offset. The control gate electrode is formed through the ON film and second gate dielectric film on the floating gate electrode. The control gate electrode is formed to cover the offset region. The first gale dielectric film is formed entirely of the tunneling dielectric film at least in the region beneath the floating gate electrode. In such constitution, an electrically erasable and programmable semiconductor memory device small in cell area and excellent in matching with other process may be obtained.

Abstract: A surface mounting type diode is provided which comprises: a diode chip; a pair of leads held in electrical conduction with the diode chip, each of the leads including an inner end, an outer end, a first bend closer to the inner end, a second bend closer to the outer end, and an intermediate portion between the first and second bends; and a resin package enclosing the diode chip together with part of the respective leads, the resin package having a flat bottom surface. The inner end, first bend, second bend and intermediate portion of the lead are contained in the resin package. Further, the outer end of the lead has an exposed flat mounting surface flush with the bottom surface of the resin package.

Abstract: A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference.

Abstract: A method for producing a low capacitance floating diffusion structure used for charge to voltage conversion in a solid state image sensor having an output amplifier provided with a gate electrode, comprising the steps of: (a) growing a gate oxide on a substrate of a given conductivity type; (b) forming the gate electrode for the output amplifier on the gate oxide and patterning the gate electrode so as to create an opening through it; (c) introducing through the opening a dopant of a conductivity type opposite to the given conductivity type so as to create a floating diffusion region in the substrate; and (d) creating an ohmic contact between the floating diffusion region and the gate electrode.

Abstract: A very large scale integrated (VLSI) chip designed to operate at 3.3 volts is modified to be compatible with prior systems having a 5 volt voltage supply. A central processing unit (CPU) is fabricated at a center position on an integrated circuit chip that has an operating voltage of 3.3 volts. The chip is soldered into a pin grid array (PGA) package and a heat sink is attached on the PGA package above the CPU. A 5 volt-to-3.3 volt voltage regulator having a 5 volt input and a 3.3 volt output is placed at an edge of the PGA package. The 3.3 volt output of the voltage regulator is connected to the 3.3 volt operating voltage input of the chip. The VCC 5 V on board pins are connected to the 5 volt input of the voltage regulator and the 3.3 volt output of the voltage regulator is connected to the VCC pins of the chip. VSS ground on board pins are connected in common to both the ground terminal of the voltage regulator and the VSS pads of the chip.

Abstract: A manufacturable III-V semiconductor gate structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.

Abstract: A multilayered interconnection substrate which prevents contact failure from occurring and a process for fabricating the same, said multilayered interconnection substrate comprising a first interconnection layer formed on a substrate, at least two layers of insulation films differing in composition from each other and being formed on said first interconnection layer, provided that the insulation layers comprise at least one contact hole formed in such a manner to expose the selected portion of said first interconnection layer, a resin wall which buries the stepped portions formed on the inner peripheral portion of said contact hole, and a second interconnection layer formed inside said contact hole along said resin wall and being electrically connected to the first interconnection layer exposed at the bottom portion of the contact hole.

Abstract: A semiconductor device comprising a source region, a channel region, and a drain region, provided that one or both of the phase boundary between the channel forming region and the source region and that between the channel forming region and the drain region are shaped into an uneven shape, and optionally, periodically. Also claimed is a process for fabricating the same.

Abstract: A new Schottky diode structure, Pt/Al/n-InP, is disclosed in the present invention. The thickness of Al layer of the Schottky diode structure is restricted in a range of about 80-120 .ANG.. This structure gives a barrier height of 0.74 eV and an ideality factor of 1.11 after it was annealed at 300.degree. C. for 10 min. This is due to the formation of Aluminum-oxide, as the interfacial layer to improve barrier height. A method of preparing this Schottky diode structure is also disclosed in the present invention.

Abstract: A semiconductor device that includes a wiring line formed from an electrode wiring layer which uses, as an electrode material, an Al alloy containing Cu, wherein wiring line having a size smaller than a crystal grain diameter has a Cu concentration of 0.05 to 0.3 wt %, and a wiring line having a size larger than a crystal grain diameter has a Cu concentration of 0.5 to 10 wt %.

Abstract: Stringers and depth of focus problems in substrates having above-surface isolation schemes are avoided by applying a first portion of a gate conductor over the entire surface having above-surface isolation, selectively removing the gate conductor from above the isolation features of the above-surface isolation, and overcoating the entire surface with a second portion of gate conductor. The process has particular application to substrates that employ regions having field-shield isolation. An important feature of the invention is drawn to creating structures wherein gate conductor is applied to a substrate including both above-surface and below-surface isolation regions in a manner which leaves the gate conductor planarized over both the above-surface and below-surface regions.

Abstract: Undercutting of conductive lines in a dense array on a dielectric layer containing an open field is prevented by providing one or more non-functional components, such as one or more non-functional conductive lines, in the dielectric layer under the dense array of conductive lines.