Patents Examined by Nathan W. Ha
  • Solid-state imaging device, method of manufacturing a solid-state imaging device, and electronic apparatus
    Patent number: 10367027
    Abstract: Disclosed is a solid-state imaging device including a plurality of pixels and a plurality of on-chip lenses. The plurality of pixels are arranged in a matrix pattern. Each of the pixels has a photoelectric conversion portion configured to photoelectrically convert light incident from a rear surface side of a semiconductor substrate. The plurality of on-chip lenses are arranged for every other pixel. The on-chip lenses are larger in size than the pixels. Each of color filters at the pixels where the on-chip lenses are present has a cross-sectional shape whose upper side close to the on-chip lens is the same in width as the on-chip lens and whose lower side close to the photoelectric conversion portion is shorter than the upper side.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 30, 2019
    Assignee: Sony Corporation
    Inventors: Rena Suzuki, Hiroki Tojinbara, Ryoto Yoshita, Yoichi Ueda
  • Flexible and stretchable sensors formed by patterned spalling
    Patent number: 10365240
    Abstract: A material removal process referred to as spalling is used to provide flexible and stretchable sensors that can be used for healthcare monitoring, bio-medical devices, wearable electronic devices, artificial skin, large area sensing, etc. The flexible and stretchable sensors of the present application have high sensitivity that is comparable to that of a bulk silicon sensor. The flexible and stretchable sensors comprise single crystalline spring-like structures that couple various resistor structures together.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Shu-Jen Han, Ning Li, Devendra K. Sadana
  • Forming insulator fin structure in isolation region to support gate structures
    Patent number: 10347537
    Abstract: A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active device region and an isolation region. The composite fin structures may include a semiconductor portion over the active device region and a dielectric portion over the isolation region. A gate structure can be formed on the channel region of the fin structures that are present on the active regions of the substrate, and the gate structure is also formed on the dielectric fin structures on the isolation regions of the substrate. Epitaxial source and drain regions are formed on source and drain portions of the fin structures present on the active region, wherein the dielectric fin structures support the gate structure over the isolation regions.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Peng Xu
  • Display device
    Patent number: 10325871
    Abstract: A display device comprises a control circuit board generating a first control signal; a driver chip package connected to the control circuit board and receiving the first control signal; and a display panel connected to the driver chip package interconnecting the control circuit board and the display panel. The display panel comprises pixels formed and signal lines connected to the pixels. The driver chip package comprises a wire film and a driver chip attached over the wire film. The driver chip is fixed to the display panel to transfer the second control signal to at least one of the plurality of signal lines. The wire film interconnects the driver chip and the control circuit board to transfer the first control signal from the control circuit board to the driver chip.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hae-Kwan Seo
  • Electrode for a metal-insulator-metal structure, capacitor of metal-insulator-metal type, and method for fabricating one such electrode and one such capacitor
    Patent number: 10319806
    Abstract: The electrode for a structure of Metal-Insulator-Metal type is formed by a stack successively comprising a gold layer, a barrier layer made from electrically conducting oxide and a platinum layer. The electrically conducting oxide is advantageously a noble metal oxide, and preferentially ruthenium oxide. The electrode is arranged on a substrate. The gold layer of the electrode is separated from the substrate by an adhesion layer made from titanium dioxide. The electrode is used to fabricate a capacitor of Metal-Insulator-Metal type.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: June 11, 2019
    Assignees: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Guillaume Rodriguez, Aomar Halimaoui, Laurent Ortiz
  • Power circuit and power module using MISFET having control circuit disposed between gate and source
    Patent number: 10320380
    Abstract: The power circuit includes: a main substrate; a first electrode pattern disposed on the main substrate and connected to a positive-side power terminal P; a second electrode pattern disposed on a main substrate and connected to a negative-side power terminal N; a third electrode pattern disposed on the main substrate and connected to an output terminal O; a first MISFET Q1 of which a first drain is disposed on the first electrode pattern; a second MISFET Q4 of which a second drain is disposed on the third electrode pattern; a first control circuit (DG1) connected between a first gate G1 and a first source S1 of the first MISFET, and configured to control a current path conducted from the first source towards the first gate.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: June 11, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Hirotaka Otake, Tatsuya Yanagi, Yusuke Nakakohara
  • Antenna assembly for wafer level packaging
    Patent number: 10319689
    Abstract: Embodiments are provided for a packaged semiconductor device that includes a package substrate that in turn includes an embedded die configured to process a radio frequency (RF) signal; a printed circuit board (PCB) attached to a front side of the package substrate, where the PCB includes a cavity; and an antenna enabling element attached to the front side of the package substrate within the cavity, the antenna enabling element configured to convey the RF signal through the cavity.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Weng Foong Yap, Jinbang Tang
  • Semiconductor pressure sensor for harsh media application
    Patent number: 10308502
    Abstract: A semiconductor pressure sensor assembly for measuring a pressure of an exhaust gas which contains corrosive components, comprising: a first cavity, a pressure sensor comprising first bondpads for electrical interconnection, a CMOS chip comprising second bondpads for electrical interconnection with the pressure sensor, an interconnection module having electrically conductive paths connected via bonding wires to the pressure sensor and to the CMOS chip; the interconnection module being a substrate with corrosion-resistant metal tracks, wherein the CMOS chip and part of the interconnection module are encapsulated by a plastic package.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: June 4, 2019
    Assignee: MELEXIS TECHNOLOGIES NV
    Inventors: Laurent Otte, Jian Chen, Appolonius Jacobus Van Der Wiel
  • Self-aligned shallow trench isolation and doping for vertical fin transistors
    Patent number: 10312371
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Fee Li Lie, Junli Wang
  • High voltage device
    Patent number: 10312379
    Abstract: A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: June 4, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kai-Kuen Chang, Ching-Chung Yang
  • Forming insulator fin structure in isolation region to support gate structures
    Patent number: 10304742
    Abstract: A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an active device region and an isolation region. The composite fin structures may include a semiconductor portion over the active device region and a dielectric portion over the isolation region. A gate structure can be formed on the channel region of the fin structures that are present on the active regions of the substrate, and the gate structure is also formed on the dielectric fin structures on the isolation regions of the substrate. Epitaxial source and drain regions are formed on source and drain portions of the fin structures present on the active region, wherein the dielectric fin structures support the gate structure over the isolation regions.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Peng Xu
  • Chip package structure and method for forming the same
    Patent number: 10283474
    Abstract: A method for forming a chip package structure is provided. The method includes forming a first dielectric layer over a carrier substrate. The first dielectric layer is a continuous dielectric layer and has openings. The method includes forming a first wiring layer over the first dielectric layer and in the openings. The first dielectric layer and the first wiring layer together form a redistribution structure, and the redistribution structure has a first surface and a second surface. The method includes disposing a first chip and a first conductive bump over the first surface. The method includes forming a first molding layer over the first surface. The method includes removing the carrier substrate. The method includes disposing a second chip and a second conductive bump over the second surface. The method includes forming a second molding layer over the second surface.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu
  • Method of forming trenches with different depths
    Patent number: 10283403
    Abstract: A semiconductor device includes a gate structure disposed over a substrate, and a first dielectric layer disposed over the substrate, including and over the gate structure. A first metal feature is disposed in the first dielectric layer, including an upper portion having a first width and a lower portion having a second width that is different than the first width. A dielectric spacer is disposed along the lower portion of the first metal feature, wherein the upper portion of the first metal feature is disposed over the dielectric spacer. A second dielectric layer is disposed over the first dielectric layer, including over the first metal feature and a second metal feature extends through the second dielectric layer to physically contact with the first metal feature. A third metal feature extends through the second dielectric layer and the first dielectric layer to physically contact the gate structure.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Hsun Wang, Hsien-Cheng Wang, Mei-Yun Wang
  • Circuit package
    Patent number: 10276468
    Abstract: A circuit package comprises a circuit device in a first epoxy mold compound and a second epoxy mold compound of different compositions.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: April 30, 2019
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Chien-Hua Chen, Michael W Cumbie, Stephen Farrar
  • Material deposition for high aspect ratio structures
    Patent number: 10276369
    Abstract: Ion species are supplied to a workpiece comprising a pattern layer over a substrate. A material layer is deposited on the pattern layer using an implantation process of the ion species. In one embodiment, the deposited material layer has an etch selectivity to the pattern layer. In one embodiment, a trench is formed on the pattern layer. The trench comprises a bottom and a sidewall. The material layer is deposited into the trench using the ion implantation process. The material layer is deposited on the bottom of the trench in a direction along the sidewall.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: April 30, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Jun Xue, Ludovic Godet, Martin A. Hilkene, Matthew D. Scotney-Castle
  • Package structure, electronic device and method of fabricating package structure
    Patent number: 10276920
    Abstract: In accordance with some embodiments, a package structure includes an RFIC chip. an insulating encapsulation, a redistribution circuit structure, an antenna and a microwave director. The insulating encapsulation encapsulates the RFIC chip. The redistribution circuit structure is disposed on the insulating encapsulation and electrically connected to the RFIC chip. The antenna is disposed on the insulating encapsulation and electrically connected to the RFIC chip through the redistribution circuit structure. The antenna is located between the microwave director and the RFIC chip. The microwave director has a microwave directivity enhancement surface located at a propagating path of a microwave received or generated by the antenna.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Chien Hsiao, Chen-Hua Yu, Chung-Shi Liu, Chao-Wen Shih, Shou-Zen Chang
  • Solid-state imaging device and imaging apparatus
    Patent number: 10271023
    Abstract: The present technique relates to a solid-state imaging device and an imaging apparatus that enable provision of a solid-state imaging device having superior color separation and high sensitivity.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: April 23, 2019
    Assignee: Sony Corporation
    Inventor: Tetsuji Yamaguchi
  • Semiconductor device having structure for improving voltage drop and device including the same
    Patent number: 10249569
    Abstract: A semiconductor device includes a semiconductor substrate and a plurality of metal layers above the semiconductor substrate. A first of the metal layers includes a plurality of first power rails which extend in a first direction and provide a first voltage, a plurality of second power rails which extend in the first direction and provide a second voltage, and a first conductor which is integral with one end of each of the first power rails and extends in a second direction. The first direction is perpendicular to the second direction. The first voltage is one of a ground voltage and a power source voltage and the second voltage is the other voltage.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 2, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sung Su Byun
  • Light-emitting display panel
    Patent number: 10249844
    Abstract: A light-emitting display panel is provided. The light-emitting display panel includes a substrate. The substrate includes a display area and a peripheral area surrounding the display area. A light-emitting display structure is disposed on the display area. A first section wall is disposed on the peripheral area. The first section wall surrounds the light-emitting display structure. An enclosed wall is disposed on the peripheral area. The enclosed wall surrounds the first section wall. The enclosed wall is positioned outside the first section wall. A first inorganic material layer covers the light-emitting display structure. The first inorganic material layer covers the top surface of the array substrate outside the enclosed wall.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: April 2, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Cheng-Hsu Chou, Yi-Xin Yang
  • Semiconductor die bond pad with insulating separator
    Patent number: 10249583
    Abstract: A semiconductor die includes a last metallization layer above a semiconductor substrate, a bond pad above the last metallization layer, a passivation layer covering part of the bond pad and having an opening that defines a contact area of the bond pad, an insulating region separating the bond pad from the last metallization layer at least in an area corresponding to the contact area of the bond pad, and an electrically conductive interconnection structure that extends from the bond pad to the upper metallization layer outside the contact area of the bond pad. Corresponding methods of manufacture are also provided.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Christian Bretthauer, Bernhard Laumer, Holger Poehle, Momtchil Stavrev