Abstract: A semiconductor package includes: a first structure including a plurality of stacked first semiconductor chips and electrically connected to a first redistribution layer through connection vias having different heights; and a second structure including a second semiconductor chip electrically connected to a second redistribution layer. The first and second redistribution layers are electrically connected to each other through an electrical connection member formed on the second structure.

Abstract: A thin film encapsulation structure included in an organic EL display apparatus includes a first inorganic barrier layer, an organic barrier layer in contact with the inorganic barrier layer, and a second inorganic barrier layer in contact with the organic barrier layer. The thin film encapsulation structure is formed on an active region and the active region side portion of a plurality of lead wires extending from the active region to a terminal. Each of the lead wires at least partially includes, at at least the lowermost portions of two side surfaces thereof in contact with the first inorganic barrier layer, a forward tapering side surface portion having a tapering angle smaller than 90 degrees in a cross-section parallel to a line width direction thereof. The thin film encapsulation structure includes an inorganic barrier layer joint portion in which the organic barrier layer is not present, and the first inorganic barrier layer and the second inorganic barrier layer are in direct contact with each other.

Abstract: A semiconductor device including multiple fins. At least a first set of fins among the multiple fins is substantially parallel. At least a second set of fins among the multiple fins is substantially collinear. For any given first and second fins of the multiple fins having corresponding first and second fin-thicknesses, the second fin-thickness is less than plus or minus about 50% of the first fin-thickness.

Abstract: An organic EL display device including: a base substrate; an organic EL element formed on the base substrate, and including a plurality of organic EL layers arranged in a matrix shape; and a sealing film formed on the organic EL element, wherein a plurality of subpixels are defined in association with the plurality of organic EL layers, and a plurality of grooves are formed in the sealing film through the interstices among the plurality of subpixels, and a foreign-matter contact portion configured to be in contact with a foreign matter existing on the organic EL element is formed in the sealing film.

Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

Abstract: The present technique relates to a solid-state imaging device and an imaging apparatus that enable provision of a solid-state imaging device having superior color separation and high sensitivity. The solid-state imaging device includes a semiconductor layer in which a surface side becomes a circuit formation surface, photoelectric conversion units PD1 and PD2 of two layers or more that are stacked and formed in the semiconductor layer, and a longitudinal transistor Tr1 in which a gate electrode is formed to be embedded in the semiconductor layer from a surface of the semiconductor layer. The photoelectric conversion unit PD1 of one layer in the photoelectric conversion units of the two layers or more is formed over a portion of the gate electrode of the longitudinal transistor Tr1 embedded in the semiconductor substrate and is connected to a channel formed by the longitudinal transistor Tr1.

Abstract: A method for manufacturing a module including N layers of stacked resin is provided, wherein N is a natural number of two or more. In the method, resin of a first layer is cured to a degree that does not fully harden the resin of the first layer. Resin of a Mth layer is stacked on resin of a (M?1)th layer, wherein M is a natural number of two or more and less than N. The resin of the Mth layer is cured to a degree that does not fully harden the resin of the Mth layer. Stacking the resin of the Mth layer and curing the resin of the Mth layer are repeated. Then, resin of Nth layer is stacked, and all of the N layers of stacked resin are fully hardened.

Abstract: Certain aspects of the present disclosure generally relate to a transistor having an implant region for reducing a net doping concentration below an edge of a gate region of the transistor. One example transistor generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the first semiconductor region being between and having a different doping type than the second semiconductor region and the third semiconductor region. In certain aspects, the transistor also includes a gate dielectric layer disposed above the first semiconductor region, a non-insulative region disposed above the gate dielectric layer, and an implant region disposed above the second semiconductor region, the implant region having a different doping type than the second semiconductor region.

Abstract: The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of reducing the uppermost semiconductor chip damage and stably performing wire bonding even if an excessive force is applied during a die bonding process or a wire bonding process, and a method for manufacturing the semiconductor device.

Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit formed on the substrate includes a plurality of protection diodes that are connected in series with each other, and the protection circuit is connected to an output terminal of the amplifier circuit. A pad conductive layer at least partially includes a pad for connecting to a circuit outside the substrate. The pad conductive layer and the protection circuit at least partially overlap each other in plan view.

Abstract: There is provided a semiconductor device that enables a semiconductor module that connects a wiring substrate and a semiconductor chip mounted on the wiring substrate via a circuit element and that has reduced a wiring length to improve transmission quality of signals or the like so as to achieve miniaturization of the semiconductor module. The semiconductor device includes a wiring substrate, a semiconductor chip disposed on an upper surface of the wiring substrate, a resin portion formed between the wiring substrate and the semiconductor chip, and a circuit element embedded in the resin portion. The circuit element includes a first terminal connected to wiring formed on the upper surface of the wiring substrate, and a second terminal connected to a bump provided on a lower surface of the semiconductor chip.

Abstract: A circuit package comprises a circuit device in a first epoxy mold compound and a second epoxy mold compound of different compositions.

Abstract: The present invention provides a TFT that has a channel length particularly longer than that of an existing one, specifically, several tens to several hundreds times longer than that of the existing one, and thereby allowing turning to an on-state at a gate voltage particularly higher than the existing one and driving, and allowing having a low channel conductance gd. According to the present invention, not only the simple dispersion of on-current but also the normalized dispersion thereof can be reduced, and other than the reduction of the dispersion between the individual TFTs, the dispersion of the OLEDs themselves and the dispersion due to the deterioration of the OLED can be reduced.

Abstract: The semiconductor device has the CSP structure, and may include a plurality of electrode pads formed on a semiconductor integrated circuit in order to input/output signals from/to exterior; solder bumps for making external lead electrodes; and rewiring. The solder bumps may be arranged in two rows along the periphery of the semiconductor device. The electrode pads may be arranged inside the outermost solder bumps so as to be interposed between the two rows of solder bumps. Each trace of the rewiring may be extended from an electrode pad, and may be connected to any one of the outermost solder bumps or any one of the inner solder bumps.

Abstract: An apparatus including a semiconductor substrate; an absorption layer coupled to the semiconductor substrate, the absorption layer including a photodiode region configured to absorb photons and to generate photo-carriers from the absorbed photons; one or more first switches controlled by a first control signal, the one or more first switches configured to collect at least a portion of the photo-carriers based on the first control signal; and one or more second switches controlled by a second control signal, the one or more second switches configured to collect at least a portion of the photo-carriers based on the second control signal, where the second control signal is different from the first control signal.

Abstract: A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. The work-function metal layer has a first thickness. A pre-treatment process of the work-function metal layer may then performed, where the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer to form a treated work-function metal layer. The treated work-function metal layer has a second thickness less than the first thickness. In various embodiments, after performing the pre-treatment process, another metal layer is deposited over the treated work-function metal layer.

Abstract: Embodiments of an RF amplifier package include a body section comprising an upper surface having first and second opposing edge sides, and a die pad vertically recessed beneath the upper surface and comprising first and second opposing sides and a third side intersecting with the first and second sides. Embodiments also include first and second leads disposed on the upper surface, the second lead extending from adjacent to the second side to the second edge side; and a biasing strip connected to the second lead and disposed on the upper surface adjacent to the third side. Other embodiments include packaged RF amplifiers comprising an RF amplifier package, and an RF transistor mounted on the die pad and comprising: a control terminal electrically coupled to the first lead, a reference potential terminal directly facing and electrically connected to the die pad, and an output terminal electrically connected to the second lead.

Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.

Abstract: The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.