Abstract: A semiconductor device includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first gate insulator, a first source region and a first drain region, a pair of lightly doped drain (LDD) regions that are each shallower than the first source region and the first drain region, and a first gate electrode. The second transistor includes a second gate insulator, a second source region and a second drain region, a pair of drift regions that encompass the second source region and the second drain region respectively, and a second gate electrode, and the third transistor comprises a third gate insulator, a third source region and a third drain region, and a pair of drift regions that encompass the third source and the third drain regions respectively, and a third gate electrode. The second gate insulator is thinner than the other gate insulators.

Abstract: The disclosure provides an apparatus for preventing an integrated circuit (IC) structure from entering a latch-up mode. In an embodiment, the apparatus may include: a p-type substrate; an n-well within the p-type substrate; an n-type region within the p-type substrate, the n-type region being distinct from the n-well; a p-type region within the n-well; a power supply electrically coupled to the p-type region within the n-well; and a directional diode electrically coupling the power supply to the n-well in parallel with the p-type region. The directional diode biases a current flow from the power supply to the n-well, and the directional diode contacts the n-well distal to the p-type region.

Abstract: A semiconductor structure including an insulating encapsulant, a plurality of semiconductor dies separately embedded in the insulating encapsulant, and an electrical communication path is provided. The electrical communication path includes at least one turning wiring connected to a conductive terminal of one of the semiconductor dies and extending across and above the insulating encapsulant to reach another conductive terminal of another one of the semiconductor dies. A layout area of the at least one turning wiring is within a region corresponding to an edge of one of the semiconductor dies and a closest edge of the adjacent one of the semiconductor dies.

Abstract: A method for fabricating bipolar junction transistor (BJT) includes the steps of: providing a substrate having an emitter region, a base region, and a collector region; performing a first implantation process to form a first well region in the base region; and performing a second implantation process to form a second well region in the emitter region. Preferably, the first well region and the second well region comprise different concentration.

Abstract: A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Abstract: Methods and structures are provided for implementing strain sensing thermal interface materials (TIMs). An in situ strain sensing thermal interface material (TIM) layer is provided within a packaging assembly structure. The strain sensing TIM is formed by graphene incorporated into the TIM layer. Electrical leads are coupled to the strain sensing TIM layer providing electrical contacts for measuring the electrical property change of the TIM which correlates to mechanical strain.

Abstract: A light-emitting display panel is provided. The light-emitting display panel includes a substrate. The substrate includes a display area and a peripheral area surrounding the display area. A light-emitting display structure is disposed on the display area. A first section wall is disposed on the peripheral area. The first section wall surrounds the light-emitting display structure. An enclosed wall is disposed on the peripheral area. The enclosed wall surrounds the first section wall. The enclosed wall is positioned outside the first section wall. A first inorganic material layer covers the light-emitting display structure. The first inorganic material layer covers the top surface of the array substrate outside the enclosed wall.

Abstract: A solid-state imaging device includes a semiconductor layer on which a plurality of pixels are arranged along a light-receiving surface being a main surface of the semiconductor layer, photoelectric conversion units provided for the respective pixels in the semiconductor layer, and a trench element isolation area formed by providing an insulating layer in a trench pattern formed on a light-receiving surface side of the semiconductor layer, the trench element isolation area being provided at a position displaced from a pixel boundary between the pixels.

Abstract: A test element group includes a test element including a plurality of test transistors connected in series between a first node and a second node, the second node being connected to a ground node; a first transistor connected between the first node and a power supply node; and a second transistor configured to generate an output current, proportional to a voltage at the first node, and connected to the first node and the power supply node.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.

Abstract: A method for making a hydrophobic biosensing device includes forming alternating layers over a top and sides of a fin on a dielectric layer to form a stack of layers. The stack of layers are planarized to expose the top of the fin. The fin and every other layer are removed to form a cathode group of fins and an anode group of fins. A hydrophobic surface on the two groups of fins.

Abstract: Monolithic pixels are implemented by laterally disposed green, blue and red micro-LED sub-pixels separated by dielectric sidewalls. The green and blue sub-pixels are formed with nitride-based material layers while the red sub-pixel is formed with non-nitride-based material layers that yield an optically-efficient red sub-pixel that is intensity-balanced with the green and blue sub-pixels.

Abstract: A method includes depositing a magnetic track layer on a seed layer, depositing an alloy layer on the magnetic track layer, depositing a tunnel barrier layer on the alloy layer, depositing a pinning layer on the tunnel barrier layer, depositing a synthetic antiferromagnetic layer spacer on the pinning layer, depositing a pinned layer on the synthetic antiferromagnetic spacer layer and depositing an antiferromagnetic layer on the pinned layer, and another method includes depositing an antiferromagnetic layer on a seed layer, depositing a pinned layer on the antiferromagnetic layer, depositing a synthetic antiferromagnetic layer spacer on the pinned layer, depositing a pinning layer on the synthetic antiferromagnetic layer spacer, depositing a tunnel barrier layer on the pinning layer, depositing an alloy layer on the tunnel barrier layer and depositing a magnetic track layer on alloy layer.

Abstract: A semiconductor device comprising a pn junction diode and a method of making the same. The device includes a semiconductor substrate having a first conductivity type. The device also includes a buried oxide layer located in the substrate. The device further includes a semiconductor region having a second conductivity type extending beneath the buried oxide layer to form a pn junction with a semiconductor region having the first conductivity type. The pn junction is located beneath the buried oxide layer and extends substantially orthogonally with respect to a major surface of the substrate. The device also includes a field plate electrode comprising a semiconductor region located above the buried oxide layer for modifying an electric field at the pn junction by application of a potential to the field plate electrode.

Abstract: An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage. In addition or alternatively, an integrated circuit can include minimum feature size transistors; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein the first or second transistor is a tipless transistor.

Abstract: A semiconductor device having enhanced thermal transfer includes at least one die, including a device layer in which one or more functional circuit elements are formed and a substrate supporting the device layer, and a support structure. The die is disposed on the support structure using at least one connection structure coupled between the device layer and the support structure. A back surface of the substrate is textured so as to increase a surface area of the back surface to thereby enhance thermal transfer between the substrate and an external environment.

Abstract: A method that includes forming a conductive source/drain structure that is conductively coupled to source/drain regions of first and second transistor devices, selectively forming a conductive source/drain metallization cap structure on and in contact with an upper surface of the conductive source/drain structure, forming a patterned etch mask that exposes a portion of the gate cap and a portion of the conductive source/drain metallization cap structure, and performing at least one etching process to remove the exposed portion of the gate cap and thereafter an exposed portion of the final gate structure so as to form a gate cut opening, wherein the conductive source/drain metallization cap structure protects the underlying conductive source/drain structure during the at least one etching process.

Abstract: A semiconductor device includes a semiconductor element, an insulated substrate on which the semiconductor element is located, and an external connection terminal electrically connected to the semiconductor element via the insulated substrate. The insulated substrate includes an insulator layer, an inner conductor layer located on one side of the insulator layer and electrically connected to the semiconductor device, and an outer conductor layer located on the other side of the insulator layer. The external connection terminal includes, along a longitudinal direction of the external connection terminal, a thin section and a thick section that is thicker than the thin section, and the external connection terminal is joined to the inner conductor layer of the insulated substrate at the thin section.

Abstract: Disclosed are three-dimensional semiconductor memory devices including an electrode structure including gate electrodes stacked in a first direction, a lower pattern group including lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate, and an upper pattern group including upper vertical patterns that are in an upper portion of the electrode structure. The upper vertical patterns may be connected to the lower vertical patterns, respectively. The devices may also include two common source plugs spaced apart from each other in a second direction. The electrode structure may be between the two common source plugs. An upper portion of the lower pattern group has a first width in the second direction, an upper portion of the upper pattern group has a second width in the second direction, and the first width may be greater than the second width.

Abstract: A semiconductor device includes a substrate, a first gate structure including first gate electrodes that are vertically stacked on the substrate, first channels penetrating the first gate structure to contact the substrate, a second gate structure including a channel connection layer on the first gate structure and second gate electrodes on the channel connection layer, second channels penetrating the second gate structure to contact the first channels, respectively, and separation regions penetrating the second gate structure and the first gate structure and extending in a first direction. The second gate electrodes are vertically stacked on the channel connection layer. The channel connection layer is between the separation regions and has at least one sidewall that is spaced apart from sidewalls of the separation regions.