Abstract: An electric vehicle, EV, connector configured for charging an electric vehicle, EV, charging receptacle, said plug connector comprising: a body having a first plug end configured to be coupled to an EV charging receptacle on an electric vehicle for charging or recharging; a second power cable end configured to be coupled to a power cable, wherein the first end includes a terminal interface having one or more terminal receptacles for receiving one or more terminals positioned within the EV charging receptacle, and wherein the first end also includes a latching member positioned generally above the terminal interface, and is hingedly coupled to a part of the body to allow the latching member to move along a vertical access for coupling or decoupling the EV connector to the EV charging receptacle, and wherein the latching member is controlled by an electro mechanical manipulator provided inside the body, and arranged to control and allow the latching member to move along the vertical access.

Abstract: Disclosed are methods of generating a proximity-corrected design layout for photoresist to be used in an etch operation. The methods may include identifying a feature in an initial design layout, and estimating one or more quantities characteristic of an in-feature plasma flux (IFPF) within the feature during the etch operation. The methods may further include estimating a quantity characteristic of an edge placement error (EPE) of the feature by comparing the one or more quantities characteristic of the IFPF to those in a look-up table (LUT, and/or through application of a multivariate model trained on the LUT, e.g., constructed through machine learning methods (MLM)) which associates values of the quantity characteristic of EPE with values of the one or more quantities characteristics of the IFPF. Thereafter, the initial design layout may be modified based on at the determined quantity characteristic of EPE.

Abstract: A method of managing the charging of a battery, and an electronic device adapted to the method are provided. The method of managing the charging of a battery installed to an electronic device includes: charging the battery; obtaining an internal resistance of the charging battery; determining whether the battery is functioning based on the internal resistance; and displaying, when the battery is malfunctioning, a message related to the danger while charging the battery.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: A method of controlling a wireless power receiver. The method includes receiving, by a power receiver, power from a wireless power transmitter; receiving, from the wireless power transmitter, a time set value that is set for checking cross connection; in response to receiving the time set value, generating a power variation in the wireless power receiver by converting a load status from a first load status to a second load status; and maintaining the second load status for a time corresponding to the received time set value.

Abstract: Generating a layout of an integrated circuit chip area from a description of an integrated circuit (IC). The description includes a register-transfer-level (RTL) design. The RTL design is partitioned in large blocks for synthesis of large block synthesis (LBS) blocks. The description of the IC further includes a floorplan for the IC, wherein each LBS block to be synthesized is assigned to a respective rectilinear shape in the floorplan and the rectilinear shapes do not overlap each other.

Abstract: A system and method place unit-level components in a macro within a unit of an integrated circuit that includes two or more of the units that each include two or more of the macros. The method includes detecting white space in a congestion plot of the macro. The white space represents potential placement areas for the unit-level components. The method also includes performing wire reach analysis between sources and sinks on different sides of the macro to determine an allowable region for the unit-level components, and deriving a buffer and latch placement reservation area in which to place the unit-level components based on the white space and the allowable region.

Abstract: An electronic unit includes an electricity reception section configured to receive power transmitted using one of a magnetic field and an electric field, a secondary battery configured to be charged based on a received power received by the electricity reception section, and a state notification section configured to provide notification to outside as to a state of its own unit. A charging period during which the secondary battery is charged based on the received power and a non-charging period are set in a time-divisional manner. The state notification section notifies of the unit state based on the received power in both of the charging period and the non-charging period.

Abstract: In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.

Abstract: A method, executed by one or more processors, for optimizing placement of a logic network, includes partitioning a logic network into a set of logic partitions, launching a set of placement optimization threads that correspond to the logic partitions, and allocating memory that is accessible to the placement optimization threads to provide a globally accessible placement memory for reserving placement locations on the integrated circuit. Each placement optimization thread may be configured to conduct the operations of determining a desired location for a logic element, reserving a set of potential locations for the logic element, determining a best location from the set of potential locations, and placing the logic element to the best location. Each placement optimization thread may also be configured to release each of the potential locations that are not the best location. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Embodiments relate to physically implementing an integrated circuit design while conforming to complex design rule constraints. According to some aspects, embodiments relate to an automated method for generating shapes for correcting design rule errors such as line end-to-end spacing violations. In these and other embodiments, the automated method determines the errors post-placement and automatically generates the required shapes, taking into account additional process design rules and neighboring shapes. Some embodiments consider clusters of objects, potential legal areas between line-ends, merging of potential legal areas and generation of various shapes to produce a design rule correct layout.

Abstract: A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving a first data representative of a first design including a first sequential element configured to be evaluated in accordance with a first signal. The method further includes transforming the first data into a second data representative of a second design. The second data includes a third data associated with a second sequential element including functionality of the first sequential element and a fourth data associated with a first logic circuit. The evaluation of the second sequential element at cycle i of the hardware verification system is performed in accordance with the first logic circuit and a value of the first signal as computed during cycle i?1 of the hardware verification system when the second data is compiled for programming into the hardware verification system, where i is an integer number.

Abstract: A method for connecting a plurality of battery cells of a battery, wherein the battery cells are each electrically coupled to the battery with a corresponding first probability and are each electrically decoupled from the battery with a corresponding second probability. A first quality factor is calculated for each battery cell depending on a state of charge and on a state of ageing of the corresponding battery cell. An average first quality factor, corresponding to an average value of the first quality factors of the battery cells, is also determined. A second quality factor is calculated for each battery cell as a function of the difference between the first quality factor of the corresponding battery cell and the average first quality factor. The first probability and the second probability are determined for each battery cell based on the second quality factor of the corresponding battery cell.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using at least one processor, an electronic design and identifying at least one property violation associated with the electronic design. Embodiments may further include generating a sensitivity path from an input to the at least one property violation. Embodiments may also include analyzing the electronic design to identify one or more of a portion of the electronic design that caused the at least one property violation, a portion of the electronic design that did not cause the at least one property violation, and a portion of the electronic design that has not been analyzed. Embodiments may further include applying at least one of a depth analysis and a breadth analysis to the sensitivity path.

Abstract: An integration circuit (IC) simulation method includes: (a) providing a design netlist of a system-level circuit, wherein the system-level circuit comprises a first sub-circuit; (b) providing a first behavior model that is determined based on an operation of the first sub-circuit, wherein the first behavior model is a function of one or more respective behavior-level parameters; (c) incorporating a first variation into each of the one or more behavior-level parameters of the first behavioral model; and (d) simulating the system-level circuit based on the one or more behavior-level parameters of the first behavior model that incorporates the first variation.

Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.

Abstract: Disclosed approaches for processing a circuit design targeted to a programmable integrated circuit (IC) include inputting the circuit design to a programmed processor. Each path of the circuit design specifies a plurality of circuit elements of the programmable IC. For each circuit element specified in a path of the plurality of paths the processor looks up in a memory a mean delay associated with the circuit element, looks up a sigma factor associated with the circuit element, and looks up a delta factor associated with the circuit element. The processor determines a delay of the path as a function of the mean delay, sigma factor, and delta factor of each circuit element in the path.

Abstract: Dynamic allocation of power modules for charging electric vehicles is described herein. A power cabinet includes multiple power modules that each are capable of supplying an amount of power to a dispenser. Multiple dispensers are coupled with the same power cabinet. A first power bus couples a first dispenser and switchably connects the power modules to the first dispenser; and a second power bus couples a second dispenser and switchably connects the power modules to the second dispenser. The power cabinet includes a control unit that is configured to cause the power modules to switchably connect and disconnect from the first power bus and the second power bus to dynamically allocate the power modules between the first dispenser and the second dispenser.

Abstract: A diagnostic system for a battery system having a battery module electrically coupled to a contactor is provided. The battery module has first, second, and third battery cells. The diagnostic system includes a first microcontroller that transitions the contactor to an open operational state if the first battery cell analog overvoltage flag is equal to the first battery cell analog overvoltage flag value. The first microcontroller further transitions the contactor to the open operational state if the first battery cell comparator overvoltage flag is equal to the first battery cell comparator overvoltage flag value.

Abstract: A charging device and a control method for the charging device are provided. The charging device includes an AC/DC converting circuit and a main controller. The main controller includes a first modulation module and a second modulation module. The operation of the switching circuit controlled by the second modulation module consumes less amount of electric energy than the operation of the switching circuit controlled by the first modulation module. When the charging device is in the heavy load condition, the first modulation module is enabled to control the operation of the switching circuit. When the charging device is in the light load condition or the no load condition, the second modulation module is enabled to control the operation of the switching circuit. Consequently, the power consumption of the charging device in the light load condition or the no load condition is reduced.