Abstract: A charger of the present invention includes a charging circuit that allows a secondary battery to be charged, a state-of-charge detection circuit that detects a state of charge of the secondary battery, a pictogram display unit that displays the state of charge of the secondary battery, and a control device that controls the charging circuit and the pictogram display unit on the basis of the state of charge of the secondary battery. The control device determines a kind of electronic apparatus available by the secondary battery in accordance with the state of charge of the secondary battery, and then displays the kind of electronic apparatus available on the pictogram display unit.

Abstract: A device for servicing/maintaining a high-voltage battery, which has individual battery cells or battery modules, and high-voltage positive and negative terminals, and a battery management system having a data transmission terminal for bidirectionally transmitting management system data between the management system and an information-processing unit, external to the battery. The device includes at least two of: a battery charge device, a battery discharge device, and a battery diagnostic device. A battery charge device brings a battery to a higher charge state, and has positive and negative terminals to be connected to positive and negative battery terminals. A battery diagnostic device checks a battery, and the device, for the presence of internal errors, and to indicate recognized internal errors, and may also produce diagnostic data for the battery state and triggering functions directed to bring the device and/or battery safely into a different state, to operate/test them.

Abstract: An inductive charger alignment system for a vehicle that includes: a plurality of on-board inductive receiving coils adapted to charge an on-board power source; an alignment controller coupled to the coils; an on-board signal element, e.g., a pair of headlamps, coupled to the controller; and an off-board inductive transmitter coil. Further, the controller is configured to direct the element to communicate an alignment between the receiving coils and the transmitter coil to an on-board driver. The alignment may include vehicle forward and side-to-side alignment between the receiving coils and the off-board transmitter coil.

Abstract: A method is provided for operating a DC-DC converter (22) of a charger (20). The DC-DC converter has on a primary side a first transformation coil (28) and at least one second transformation coil (30) that are arranged in series one behind another and also alongside a secondary side transformation coil (48). A respective semiconductor switch is connected in parallel with the at least one second primary side transformation coil (30). The at least one second primary side transformation coil (30) is switched either on or off by the semiconductor switch depending on a present value of at least one operating parameter of the charger (20).

Abstract: An electronic cigarette and a method for detecting battery rod insertion into or removal from an electronic cigarette case. The electronic cigarette case is used for charging an electronic cigarette battery rod having a built-in magnet. The electronic cigarette case comprises: a microprocessor, a Hall sensor module, a battery rod charging interface and a charging circuit. The Hall sensor module is connected to the microprocessor. The charging circuit is connected to the microprocessor. The battery rod charging interface is connected to the charging circuit. The beneficial effect is that insertion or removal of a battery rod can be accurately identified on the basis of changes in a magnetic field, thus controlling the turning-on or turning-off of the charging circuit, providing a user with a novel charging scheme, better meeting customer needs, and enhancing user experience.

Abstract: This disclosure relates generally to electronic design automation using high level synthesis techniques to generate circuit designs that include safety features. The algorithmic description representation can be specified in a first language and include at least one programming language construct associated with a first safety data type. Compiling the algorithmic description may involve identifying the at least one construct, accessing a first safety data type definition associated with the first safety data type, and generating a second representation of the circuit design based on the algorithmic description representation and the first safety data type definition. The second representation can be provided in a second language and include at least one safety feature for a portion of the circuit design associated with the at least one construct.

Abstract: A layout design of a standard cell for a set of masks includes a first gate pad layout pattern, a second gate pad layout pattern immediately adjacent to the first gate pad layout pattern, and a third gate pad layout pattern immediately adjacent to the second gate pad layout pattern. Each gate pad layout pattern has first and second sides extending along a first direction, the second side further along a second direction than the first side. A first gate pad pitch is a distance between first sides of the first and second gate pad layout patterns and has a value different from that of a second gate pad pitch that is a distance between first sides of the second and third gate pad layout patterns. Each gate pad pattern is usable for forming a gate pad surrounding a set of channel structures.

Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

Abstract: A method of modeling an integrated circuit comprises generating a schematic of an integrated circuit comprising a first circuit component. The schematic comprises a first representation of the first circuit component. The method also comprises replacing the first representation with a second representation of the first circuit component. The second representation includes resistive capacitance information (RC) for the first circuit component. The RC information is based on first RC data included in a process design kit (PDK) file and second RC data included in a macro device file. The second RC data is based on a relationship between the first circuit component and a second circuit component. The method further comprises selectively coloring the second representation of the first circuit component in the schematic based on the RC information. The coloring of the second representation is indicative of whether the integrated circuit is in compliance with a design specification.

Abstract: A method for manufacturing a semiconductor device includes obtaining a design layout for a target layer of an optical proximity correction process, the design layout including a first block and a second block being a repetition block of the first block, dividing the design layout into a plurality of patches, performing the optical proximity correction process on the patches of the first block, applying corrected patches of the first block to the patches of the second block, respectively, forming a correction layout by performing the optical proximity correction process on boundary patches of the second block, fabricating a photomask corresponding to the correction layout, and forming patterns on a substrate corresponding to the photomask. Each of the patches is a standard unit on which the optical proximity correction process is performed.

Abstract: A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.

Abstract: Various embodiments include approaches for modifying a design layer of an integrated circuit (IC). In some cases, an approach includes: identifying at least one empty region in a design layer used to form the IC; determining whether the at least one empty region requires a fill object; placing at least one fill object in the at least one empty region and tagging the at least one fill object in response to determining the at least one empty region requires a fill object; performing a simplified optical proximity correction (OPC) on the tagged at least one fill object and a complete OPC on the design layer; and generating a modified design layer including a corrected version of the design layer and modified fill objects after the performing of the simplified OPC on the tagged at least one fill object and the complete OPC on the design layer.

Abstract: A computer-implemented method of fabricating an integrated circuit structure includes selecting a first cell from a standard cell library, the first cell having a cell boundary and comprising a metal segment at a first metal track at a metal layer, the metal segment extending along a direction and terminating a specified distance beyond a first edge of the cell boundary. The method further includes placing the first cell at a first location of a physical layout for the integrated circuit structure. The method also includes selecting a second cell from the standard cell library and placing the second cell at a second location of the physical layout such that a second edge of a cell boundary of the second cell abuts the first edge of the cell boundary of the first cell, and wherein the metal segment extends into a metal track at the metal layer of the second cell.

Abstract: A temperature change of a device on an integrated circuit chip due to self-heating and thermal coupling with other device(s) is modeled considering inefficient heat removal from the backside of the chip. To perform such modeling, ratios of an imaginary heat amount to an actual heat amount for different locations on the IC chip must be predetermined using a test integrated circuit (IC) chip. During testing, one test device at one specific location on the test IC chip is selected to function as a heat source, while at least two other test devices at other locations on the test IC chip function as temperature sensors. The heat source is biased and changes in temperature at the heat source and at the sensors are determined. These changes are used to calculate the value of the imaginary heat amount to actual heat amount ratio to be associated with the specific location.

Abstract: A design apparatus includes a processing unit configured to allocate a plurality of RAMs to a FPGA block RAM in at least one of a word direction and a bit direction thereof, and to generate a description, in a hardware description language, of a control circuit that controls input and output signals of each of the plurality of RAMs so as to allow each of the plurality of RAMs to be accessed as a single RAM.

Abstract: A method for designing a system on a target device includes identifying a timing exception for a portion of a signal path. An area on the target device that includes components affected by the timing exception. Register retiming is performed where pipeline registers are added at boundaries of the area.

Abstract: Aspects of the disclosed technology relate to techniques of design implementation for FPGA prototyping. An initial FPGA-mapped netlist and a generic RTL design associated with the initial FPGA-mapped netlist are generated based on an original RTL (register-transfer level) design for a circuit design and optionally on verification-related features. Based on the initial FPGA-mapped netlist, the circuit design is partitioned into design partitions for implementing the circuit design across a plurality of FPGA chips. Final FPGA-mapped netlists are then generated based on the design partitions represented by the generic RTL design or by a combination of the generic RTL design and the initial FPGA-mapped netlist.

Abstract: For a design under test (DUT) that is to be emulated, a host system partitions the DUT into multiple partitions and maps each partition to an FPGA of an emulator which will emulate the partition. The host system stores information describing to which FPGAs each component of the DUT has been mapped. Additionally, mapped to each FPGA is trace and injection logic that traces signals exchanged by the FPGA with other FPGAs during emulation of the DUT. After the emulation of the DUT is complete, if a user wishes to debug a component of the DUT, the FPGAs that are configured to emulate the component are identified. For each identified FPGA, the trace and injection logic injects previously traced signals into the logic of the FPGA in order to reemulate the component. The host system generates waveforms for the user that include signals traced during the reemulation of the component.

Abstract: A method for designing a multiple tuned filter (MTF) in a high voltage direct current (HVDC) system includes setting an input parameter constituting the MTF; setting a resonance frequency of the MTF; extracting at least one LC combination case constituting the MTF on the basis of the input parameter and the resonance frequency; performing optimization for harmonic reduction on the LC combination case; and extracting an LC combination case determined based on a result obtained by performing the optimization.

Abstract: A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit.