Abstract: A method, an apparatus, and a non-transitory computer readable medium for full chip mask pattern generation include: generating, by a processor, an initial mask image from target polygons, performing, by the processor, a global image based full chip optimization of the initial mask image to generate new mask pattern polygons, wherein the global image based full chip optimization co-optimizes main feature polygons and SRAF image pixels, determining performance index information based on the global image based full chip optimization, wherein the performance index information comprises data for assisting a global polygon optimization, generating a mask based on the global polygon optimization of the new mask pattern polygons using the performance index information, and generating optimized mask patterns based on a localized polygon optimization of the mask.

Abstract: Docking stations that may facilitate the sharing or transfer of power among a portable computing device, a docking station, and an accessory. One example may provide power from an accessory to a portable computing device. Switches may be used to avoid harm from inadvertent contact with voltages on exposed terminals. Another example may provide power directly from a battery on a portable computing device to an accessory. Another may limit this direct connection to a first type of accessory. Examples may limit a power connection to another type of accessory through a regulator. Another example may power one or more internal circuits either through a portable computing device or an accessory, depending on a mode of operation of the portable computing device.

Abstract: A modular recharging system includes an electronic device that includes an internal battery, and a removable battery pack that the electronic device can use to boost the power of its internal battery. Typically, the battery pack will have a larger battery than the internal battery of the device. Based on threshold charge levels for the internal battery, the electronic device turns on and off power from the battery pack so as to preserve the life of the battery pack. Processor interrupts generated in response to the threshold levels may also be selectively masked to reduce power consumption.

Abstract: Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

Abstract: A mobile power supply may include a charging and discharging interface, a charging and discharging circuit, a central processor, and a battery pack. The charging and discharging circuit may be configured to adjust a voltage inputted to the battery pack to charge the battery pack when the voltage inputted to the battery pack is not matched with a voltage of the battery pack, or configured to adjust a voltage output to the electronic device to charge the electronic device when the voltage outputted to the electronic device is not matched with a rated voltage of the electronic device. The central processor may be configured to control the charging and discharging circuit to charge the battery pack, supply power to or charge the electronic device.

Abstract: Various implementations described herein are directed to systems and methods for controlling physical placement of a circuit design. The systems and methods may extract state groups of the circuit design by deriving state groups from each logical hierarchy of the circuit design. At each level, available state points may be grouped by similarity and stored in a state groups collection alongside grouping terms. The systems and methods may generate a state bounds file that bounds locations of the state points in the circuit design. The state bounds file may be based on the extracted state groups and the grouping terms stored in the state groups collection. The systems and methods may control physical placement of the circuit design using the state bounds file.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing deadlock detection with formal verification techniques in an electronic design. These techniques identify one or more inputs that include at least an initial state of an electronic design and identify at least one deadlock candidate by sweeping at least a portion of a state space of the electronic design with formal verification techniques. These techniques then determine whether the at least one deadlock candidate is a real deadlock by using a second formal search with the formal verification techniques.

Abstract: A capacitance measurement test vehicle comprises multiple product layers which are used to build memories except interconnect layers, and one or more customized interconnect layers to connect memory-bit-line-under-tests (MBLUTs), memory-world-line-under-tests (MWLUTs) and memory-bit-cell-under-tests (MUTs). By introducing two transistors, one PMOS and one NMOS, at two opposite sides or the same side of a bit-line or a world-line, the capacitance of the bit-line or the world-line can be measured by a parametric tester. The PMOS device is for pumping in current, and the NMOS device is for draining out the current. By applying a non-overlapping clocked signal at the PMOS and NMOS transistors, the capacitance of bit-line, word-line and bit-cell can be measured as current signal. The PMOS and NMOS transistors are selected from on-chip transistors that are already in the memory design layout.

Abstract: A simulation method of CMP process comprises: building a CMP model, and forming a matrix table of line width logarithm-density according to the CMP model, and making each intersection of the matrix table correspond to each CMP result under the corresponding line width and density; dividing a layout into a plurality of grids, and converting the equivalent line width and density of each grid into the coordinate of line width logarithm-density in the matrix table; fitting and calculating preliminary CMP simulation results of each grid according to the coordinate of each grid in the matrix table and the CMP simulation results of its adjacent intersections of the matrix table; fitting and computing final CMP simulation results of each grid according to a related weighting factor which considers the impact of adjacent grids for the current grid on the layout; outputting the final CMP simulation results of the whole layout.

Abstract: A charging device can include an input interface for receiving electrical power from a power source and an output interface for outputting electrical power to a mobile electronic device. The charging device can include a supplemental battery. A bypass electrical pathway can couple the input interface to the output interface to pass electrical charge from the power supply through the charging device to the mobile electronic device. A charging electrical pathway can couple the input interface to the supplemental battery. A discharge electrical pathway can couple the supplemental battery to the output interface. The bypass electrical pathway can include a voltage modifier configured to modify the voltage output by the output interface. The charging device can be configured to empirically determine the power capacity of the power supply. The charging device can monitor temperatures and/or battery health information, which can be used to reduce current or disable the charging device.

Abstract: A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.

Abstract: Analysis of a first verification test suite automatically generates properties that may be directly used in a subsequent verification test suite. For example, an IP module may be verified by executing a software simulation test suite. The resulting data is accessed and analyzed to detect a set of properties of the software simulation test suite. A set of emulator-synthesizable properties are selected from the set of detected properties. The emulator-synthesizable properties are suitable for incorporation in a hardware emulation test suite used to test the SoC.

Abstract: A dummy pattern filling method, including: Step I, determining the rule of filling dummy patterns, in accordance with required DR values and isolation rules of patterns; Step II, finding out blank Fields within said layout that need to be filled with dummy patterns; Step III, by following said rule of filling dummy patterns, filling dummy patterns within blank Fields on layouts. Implementing a Smart Dummy Pattern Filling, which enables the Data Ratio (DR) of dummy patterns to come infinitely close the required DR value after completing the filling of dummy patterns.

Abstract: In an aspect, the present disclosure provides a method that comprises automatic generation of a NoC from specified topological information based on projecting NoC elements of the NoC onto a grid layout. In an aspect, the specified topological information, including specification of putting constraints on positions/locations of NoC elements and links thereof, can be input by a user in real space, and can then be projected on the grid layout.

Abstract: The battery charger (C) for electric vehicles comprises a voltage converter (DC/DC CONV), a power factor correction circuit (PFC) connected upstream of the voltage converter (DC/DC CONV), a controller circuit (PFC CNTR) operatively connected to the correction circuit (PFC) and suitable for piloting the correction circuit (PFC) for the correction of the power factor in the battery charger (C), a retroaction line (L) connected to the output of the voltage converter (DC/DC CONV) and to an input of the controller circuit (PFC CNTR), wherein the controller circuit (PFC CNTR) is suitable for varying the output voltage (VPFC) of the correction circuit (PFC) within a predefined voltage interval and according to the output voltage (VDCOUT) of the voltage converter (DC/DC CONV), in order to let the voltage converter (DC/DC CONV) operate as much as possible around the point of maximum efficiency.

Abstract: Systems, methods, and computer program products for design rules checking in which the waiver of design rules is optimized while ensuring compliant designs that are manufacturable. A first design rule and a plurality of patterns of a layout that violate the first design rule are received by a design rule waiver system. The design rule waiver system may process the first design rule to extract a plurality of descriptors that can be perturbed. The design rule waiver system may perturb an attribute associated with at least one of the plurality of descriptors extracted from the first design rule in order to define a second design rule that is satisfied by the plurality of patterns.

Abstract: Methods and systems are described for using detection coils to detect metallic or conductive foreign objects that can interfere with the wireless transfer of power from a power transmitter to a power receiver. In particular, the detection coils are targeted to foreign objects that are smaller than a power transmitter coil in the power transmitter.

Abstract: A method for assigning nets to wiring planes for generating a chip design includes executing, by a computer, a zero wire load timing session for a placed but unbufferred chip design. All nets of the chip design are set to a single wide wiring track without wiring plane assignments. A delta time delay is added to each sink of each of the nets to represent an estimated time of flight (TOF) delay. The nets wiring plane or width type for a particular pin is upgraded to a type having improved TOF characteristics. Each of the nets are compared against new predetermined slack and distance targets and new assigned wiring plane or width type determined to consume additional wiring track resources, and based on results, the upgrade is repeated or a design for session timing state for the nets is output to represent the unbufferred chip design.

Abstract: The present disclosure provides a method of performing optical proximity correction (OPC). An integrated circuit (IC) design layout is received. The design layout contains a plurality of IC layout patterns. Two or more of the plurality of IC layout patterns are grouped together. The grouped IC layout patterns are dissected, or target points are set for the grouped IC layout patterns. Thereafter, an OPC process is performed based on the grouped IC layout patterns.

Abstract: A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.