Patents Examined by Naum Levin
  • Patent number: 10892633
    Abstract: Systems and methods are described herein for providing automotive type transient protection of a solar charge source. In one embodiment, a system is provided that includes a load and a solar charge source for providing DC power to the load. The solar charge source including a solar charge controller including an automotive type transient suppression module configured to provide automotive type transient protection for the solar charge source from an automotive type transient.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 12, 2021
    Assignee: Thermo King Corporation
    Inventors: Matthew Srnec, Ryan Wayne Schumacher
  • Patent number: 10885259
    Abstract: An improved random forest model is provided, which has been trained based on silicon data generated from tests of previously fabricated chips. An input is provided to the random forest model, the input including a feature set of a pattern within a particular chip layout, the feature set identifying geometric attributes of polygonal elements within the pattern. A result is generated by the random forest model based on the input, where the result identifies a predicted attribute of the pattern based on the silicon data, and the result is generated based at least in part on determining, within the random forest model, that geometric attributes of the pattern were included in the previously fabricated chips, where the previously fabricated chips have chip layouts are different from the particular chip layout.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Bikram Baidya, John A. Swanson, Kumara Sastry, Prasad N. Atkar, Vivek K. Singh
  • Patent number: 10882409
    Abstract: An onboard charging system includes an onboard battery, a vehicle-side coupling unit, a heat exchanger, a controller, and a charger. The onboard battery that is configured to be mounted on a vehicle and used to drive the vehicle. The vehicle-side coupling unit that is configured to make a charging current path to an outside-vehicle power feeding apparatus by being coupled to an apparatus-side coupling unit of the outside-vehicle power feeding apparatus. The heat exchanger that is provided in the vehicle-side coupling unit and configured to perform heat exchange between the vehicle-side coupling unit and the apparatus-side coupling unit. The controller that is configured to perform ON/OFF control of a function of the heat exchange performed by the heat exchanger. The charger that is configured to charge the onboard battery by using the charging current path.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: January 5, 2021
    Assignee: SUBARU CORPORATION
    Inventors: Yoshiaki Nakaso, Akifumi Sugaya
  • Patent number: 10884342
    Abstract: A metrology system can be integrated within a lithographic apparatus to provide integrated metrology within the lithographic process. However, this integration can result in a throughput or productivity impact of the whole lithographic apparatus which can be difficult to predict. It is therefore proposed to acquire throughput information associated with a throughput of a plurality of substrates within a lithographic apparatus, the throughput information including a throughput parameter, and predict, using a throughput simulator, a throughput using the throughput parameter as an input parameter. The throughput simulator may be calibrated using the acquired throughput information. The impact of at least one change of a throughput parameter on the throughput of the lithographic apparatus may be predicted using the throughput simulator.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: January 5, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Martinus Gerardus Maria Johannes Maassen, Reinder Teun Plug, Kaustuve Bhattacharyya
  • Patent number: 10885249
    Abstract: A system to develop an integrated circuit includes a child placement module that places in a parent macro a child macro that contains therein a child logic circuit component. The parent macro has a first hierarchical level assigned thereto and the child macro has a lower second hierarchical level assigned thereto. The system further includes a timing analysis module and a component targeting module. The timing analysis module detects a timing fault in response to performing a first parent-level optimization process on the parent macro. The component targeting module extracts from the child macro a targeted logic circuit component and places the targeted logic circuit component in the parent macro. The timing analysis module performs a second parent-level optimization process on the parent macro that resolves the timing fault based on the placement of the targeted logic circuit component in the parent macro.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: January 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nany Kollesar, Shawn Kollesar
  • Patent number: 10878150
    Abstract: Disclosed approaches for optimizing netlist loops include associating loop optimization methods with loop patterns in a computer memory. A circuit design can be synthesized into a netlist, and netlist loops that conform to the loop patterns can be identified. For each matching netlist loop, a loop optimization method associated with the loop pattern to which the netlist loop conforms can be selected. For each netlist loop, the loop optimization method associated with the loop pattern to which the netlist loop conforms can be performed to modify logic of the netlist loop in the netlist.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 29, 2020
    Assignee: Xilinx, Inc.
    Inventor: Hossein Omidian Savarbaghi
  • Patent number: 10877380
    Abstract: A method of generating an integrated circuit includes: receiving, by a processor, a first IC design layout; replacing, by the processor, a specific region in the first IC design layout with a first difference region; performing, by the processor, an inverse lithography technology process upon a junction region between the first difference region and the first IC design layout to generate a mask data; and causing the IC to be fabricated according to the mask data.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yihung Lin, Yi-Feng Lu, Huang-Ming Wu, Chi-Ta Lu
  • Patent number: 10878152
    Abstract: Techniques for an IC design include placing latches between a source and one or more sinks in the IC design, and performing an iterative process for maximizing slack on one or more input nets and one or more output nets for each of the latches, minimizing an absolute difference of the slack. The IC design includes optimizing routing for the latches and placing a clock gating latch in the IC design designated to control a LCB of LCBs. The IC design includes placing LCB logic in the IC design to control a required number of the LCBs, and placing a local clock buffer controller in the IC design in proximity to the positions of the latches.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jose Neves, Adam Matheny, Alice Hwajin Lee
  • Patent number: 10867112
    Abstract: A method of making a mask includes computing a transmission cross coefficient (TCC) matrix for an optical system for performing a lithography process, wherein computing includes decomposing the transmission cross coefficient matrix into an ideal transmission cross coefficient (TCC) kernel set for a corresponding ideal optical system and at least one perturbation kernel set with coefficients corresponding to optical defects in the optical system, calibrating a lithography model by iteratively adjusting the lithography model based on a comparison between simulated wafer patterns and measured printed wafer patterns, and providing the calibrated lithography model, which includes an ideal TCC kernel set and the at least two perturbation kernels sets and a resist model, to a mask layout synthesis tool to obtain a synthesized mask layout corresponding to a target mask layout for manufacturing the mask using the synthesized mask layout.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsu-Ting Huang, Ru-Gun Liu, Shinn-Sheng Yu
  • Patent number: 10866197
    Abstract: Methods and systems for photomask defect dispositioning are provided. One method includes directing energy to a photomask and detecting energy from the photomask. The photomask is configured for use at one or more extreme ultraviolet wavelengths of light. The method also includes detecting defects on the photomask based on the detected energy. In addition, the method includes generating charged particle beam images of the photomask at locations of the detected defects. The method further includes dispositioning the detected defects based on the charged particle beam images generated for the detected defects.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: December 15, 2020
    Assignee: KLA Corp.
    Inventors: Vikram Tolani, Masaki Satake, Weston L. Sousa
  • Patent number: 10867096
    Abstract: An integrated circuit including an FPGA having an input to receive an input data stream which includes a first portion and a second portion, processing circuitry to generate processed data by processing only the first portion of the input data stream via a data processing operation, and an output to output the processed data. The integrated circuit further includes logic circuitry, separate from the FPGA, including an input to receive the input data stream, data alignment circuitry to temporally synchronize the second portion of the input data stream with the processing of the first portion of the input data stream via the processing circuitry, and data combining circuitry to generate an output data stream using the processed data from the FPGA and the second portion of the input data stream received from the data alignment circuitry.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: December 15, 2020
    Assignee: Flex Logix Technologies, Inc.
    Inventors: Valentin Ossman, Anthony Kozaczuk
  • Patent number: 10860773
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: December 8, 2020
    Assignee: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Patent number: 10860768
    Abstract: Disclosed herein are embodiments of tools and techniques for computing the electric coupling in terms of parasitic admittance and capacitance values between a through silicon via (TSV) and surrounding interconnect of an integrated circuit layout design. In particular embodiments, a computation of one or more admittance and capacitance values between a through-silicon-via (TSV) structure and an interconnect structure of the three-dimensional integrated circuit layout design using two or more field solvers or rule-based engines that are different from one another is performed. In addition, electrical connectivity for the coupling parasitic between a TSV and an interconnect is established. Then, a parasitic netlist representation of the three-dimensional integrated circuit layout design that includes the above parasitic element values is generated.
    Type: Grant
    Filed: September 29, 2018
    Date of Patent: December 8, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Vasileios Kourkoulos, Georgios Manetas
  • Patent number: 10859634
    Abstract: An energy storage system for a vehicle is provided. The system includes a plurality of energy storage devices that are arranged to provide output power to a vehicle and are connected in parallel with each other. A plurality of sub-relays are connected to the plurality of energy storage devices, respectively. A controller then measures the degrees of deterioration of the respective energy storage devices and selectively opens or closes the sub-relays based on the amount of output power required for a vehicle and the measured degrees of deterioration such that a sub-relay connected to an energy storage device having a low degree of deterioration is closed first.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: December 8, 2020
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: In Sung Jung, Hee Sung Moon
  • Patent number: 10852800
    Abstract: A method includes programming an FPGA based controller of a master blade with a power scheme. The master blade receives a first power management signal from the master blade and slave blades. The master blade transmits a second power management signal to itself and to the slave blades responsive to the first power management signal. The master blade receives a third power management signal from itself and the slave blades. The power scheme controls an order and delay in which the second power management signal is transmitted to the first master blade and the slave blades. The power scheme controls an order and delay in which the third power management signal is received from the master blade and the slave blades. The system can be expanded by connecting the master blades to a grand master blade and multiple grand master blades to a great grand master blade.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: December 1, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Duc Dang, Ty Doan, Pinchas Herman, Zhanhe Shi
  • Patent number: 10850634
    Abstract: Methods, systems, and devices for an external vehicle charging system. The external vehicle charging system includes a first set of inductive coils. The first set of inductive coils include a first inductive coil and a second inductive coil and are configured to provide an alternating magnetic field to one or more inductive loops of a vehicle. The external vehicle charging system includes a sensor configured to detect a position of the one or more inductive loops and a processor. The processor is configured to determine a first threshold distance between the first inductive coil and the second inductive coil to reduce or eliminate interference. The processor is configured to activate the first inductive coil and the second inductive coil so that the first inductive coil and the second inductive coil align with the one or more inductive loops based on the detected position and the first threshold distance.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: December 1, 2020
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Chi-Ming Wang, Ercan M. Dede
  • Patent number: 10855089
    Abstract: A charging control device includes a detector detecting a temperature of a battery; a controller causing the charger to stop charging the battery in response to the temperature of the battery falling outside a first range during the charging of the battery; an obtainer obtaining, from the charger, information that is capable of identifying a charging characteristic of the charger; a range setter setting the first range to be a temperature range that corresponds to the charging characteristic of the charger based on the information obtained in the obtainer.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: December 1, 2020
    Assignee: MAKITA CORPORATION
    Inventors: Tadahiko Kobayakawa, Junichi Katayama
  • Patent number: 10846454
    Abstract: In accordance with the present method and system for improving integrated circuit layout, a local process modification is calculated from simulated process response variables at a set of control points. Said modification values are incorporated into the layout constraints imposed by design rules and design intent to account for manufacturing friendliness. Solving the updated constraint equation with user specified objective function produces a new layout with increased manufacturability. The new layout may further contain data tags that enable optimal process correction to be performed on selected locations, leading to reduction in data size and mask complexity. Also in accordance with this invention, physical design tools are enhanced to read and process anisotropic design rules.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 24, 2020
    Assignee: IYM Technologies LLC
    Inventor: Qi-De Qian
  • Patent number: 10839121
    Abstract: An example method for compiling by a processor-based system includes obtaining a netlist of an application, the netlist containing program nodes and respective edges between the program nodes, the application to be implemented on a device comprising an array of data processing engines; generating a global mapping of the program nodes based on a representation of the array of data processing engines; generating a detailed mapping of the program nodes based on the global mapping, the detailed mapping assigning input/outputs of programmable logic (PLIOs) of the device to channels in an interface of the array of data processing engines, the detailed mapping further assigning buffers of the application to individual memory banks in the array of data processing engines; and translating the detailed mapping to a file.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 17, 2020
    Assignee: XILINX, INC.
    Inventors: Abhishek Joshi, Grigor S. Gasparyan
  • Patent number: 10839124
    Abstract: Interactive compilation of software to a hardware language may be performed to satisfy formal verification constraints. Source code for software to be executed on a hardware design may be received. Intermediate code may be generated from the source code as part of translating the source code to a hardware language used to specify the hardware design. The intermediate code may be provided via an interface and updates to the intermediate code may be received. The updated source code may then be used to complete translation of the source code to the hardware language.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: November 17, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Uri Leder, Adi Habusha, Ofer Naaman, Tzachi Zidenberg, Ohad Gdalyahu