Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.

Abstract: A quantum computing service may store, in a cache, one or more compiled files of respective quantum functions included in one or more quantum computing programs received one or more customers. When the quantum computing service receives another quantum computing program, from the same or a different customer, the quantum computing service may determine whether the quantum computing program may include one or more of the quantum functions corresponding to the compiled files in the cache. If so, the quantum computing service may use the compiled files in the cache to compile the quantum computing program.

Abstract: Provided is a battery charging system, comprising (a) at least one charging circuit to charge at least one rechargeable battery cell; and (b) a heating device to provide heat that is transported through a heat spreader element, implemented fully outside the battery cell, to heat up the battery cell to a desired temperature Tc before or during battery charging. The system may further comprise (c) a cooling device in thermal contact with the heat spreader element configured to enable transporting internal heat of the battery cell through the heat spreader element to the cooling device when the battery cell is discharged. Charging the battery at Tc enables completion of the charging of the battery in less than 15 minutes, typically less than 10 minutes, and more typically less than 5 minutes without adversely impacting the battery structure and performance. Also provided is a battery module or pack working with such a system.

Abstract: The present disclosure relates to a chip placed in a full-custom layout and an electronic device for implementing a mining algorithm. There is provided a chip placed in a full-custom layout, comprising a pipeline structure having a plurality of operation stages, wherein each operation stage includes: a plurality of rows arranged sequentially in an X-direction parallel to a substrate of the chip and having a uniform row height in the X-direction, the plurality of rows including rows of a first type, each row of the first type including: a first set of register modules; and a first set of logical operation modules; wherein the first set of register modules and the first set of logical operation modules are adjacently provided in a Y-direction, and the first set of logical operation modules is used for processing data in the first set of register modules.

Abstract: This disclosure relates to methods of constructing efficient quantum circuits for Clifford loaders and variations of these methods following a similar scheme.

Abstract: In general, techniques are described that are directed to a device that includes a power storage device, an electrical load, and a first regulated power converter including components configured to generate, during a first time period and using electrical energy received from a power source external to the device, a first power signal to charge the power storage device. A second regulated power converter includes components configured to determine a charging current at which to charge the power storage device, determine a total amount of current flowing to the power storage device that includes current sourced by the second power converter less current sinked by the electrical load, and generate, during a second time period that is non-overlapping with the first time period, using electrical energy from the power source and based on determined the total amount of current, a second power signal to charge the power storage device.

Abstract: According to some embodiments, a rail transport vehicle electric energy storage and charging system is presented. The system may include an energy storage sub-system and a charging system having a charging rail which only charges a vehicle when the rail is covered. The system may also include a battery-powered rail vehicle having a rail-contacting charging shoe.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.

Abstract: A method is provided and includes several operations: forming a first group of macros in a first region, wherein the first group of macros are aligned with a first boundary of a channel that is coupled thereto through pins of the first group of macros; forming a second group of macros in the first region to align with a second boundary of the channel that is coupled thereto through pins of the second group of macros, wherein the first and second groups of macros are coupled to a first register; and forming a third group of macros in a second region different from the first region. A first macro and a second macro that are in the third group of macros are aligned with the first and second boundaries respectively. The third group of macros are coupled to a second register different from the first register.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.

Abstract: The invention concerns an electrical vehicle charging station for at least one electric vehicle in a network including at least a house, energy producers, and energy consumers.

Abstract: Systems, methods and devices are provided, which can include an engineering change order (ECO) base. A base layout cell includes metal layer regions, conductive gate patterns arranged above metal layer regions; oxide definition (OD) patterns, metal-zero layer over oxide-definition (metal-zero) patterns, at least one cut metal layer (CMD) pattern; and at least one via region. The base layout cell can be implemented in at least two non-identical functional cells. A first functional cell of the at least two non-identical functional cells includes first interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a first layout, and a second functional cell of the at least two non-identical functional cells includes second interconnection conductive patterns arranged connecting metal-zero structures corresponding to at least two metal-zero patterns in a second layout.

Abstract: A placement method for integrated circuit design is provided. Each net is considered as a soft module. The net will receive a larger penalty if it covers more routing congested regions. Therefore, it is easier to move the nets away from routing congested regions. In addition, to relieve local congestion, a novel inflation method is proposed to expand the area of a cluster according to its internal connectivity intensity and routing congestion occupied by the cluster. Accordingly, it can get better routability and wirelength.

Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.

Abstract: The present disclosure provides a terminal device includes: a first Type-C interface the first Type-C interface includes a first group of pins and a second group of pins. In a case where grounding impedance value of the first group of pins is within a preset range, a controller controls the first switch unit to connect the first group of pins to the application processor earphone interface, and controls the second switch unit to connect the second group of pins to the application processor fast charge interface; or in a case where the grounding impedance value of the second group of pins is within the preset range, the controller controls the second switch unit to connect the second group of pins to the application processor earphone interface, and controls the first switch unit to connect the first group of pins to the application processor fast charge interface.

Abstract: Systems and apparatuses include a vehicle controller and a mobile battery charging device. The vehicle controller is engaged with a vehicle that includes a battery charging port coupled to a vehicle battery system. The controller is configured to communicate information indicative of a state of charge of a battery of the vehicle over a network. The mobile a battery charging device includes a drive system configured to propel the battery charging device, a charging interface configured to engage the battery charging port of the vehicle, and a controller. The controller is configured to receive the information of the state of charge of the battery system of the vehicle, determine a position of the vehicle, and command the drive system to move the battery charging device to align the charging interface with the battery charging port of the vehicle to charge the battery system of the vehicle.

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

Abstract: The present disclosure relates to a chip design layout process. More specifically, the present disclosure is directed to an incremental routing-based pin assignment technique. One example method generally includes: performing routing and pin assignment for a chip design layout, one or more objects of the chip design layout being associated with a routing engine and a pin assignment engine stored in memory; detecting a change associated with the one or more objects of the chip design layout; updating, via one or more processors, at least one of the routing engine or the pin assignment engine stored in the memory in response to the detected change and based on the association between the one or more objects and the routing engine or pin assignment engine; and performing another routing and pin assignment based on the updated at least one of the routing engine or the pin assignment engine.

Abstract: The present disclosure provides a standard cell template and a semiconductor structure. The standard cell template includes a first well region and a second well region, arranged along a first direction; a first gate pattern, located in the first well region and extending along the first direction, for defining a first gate; a second gate pattern, located in the second well region and extending along the first direction, for defining a second gate; and a gate electrical connection pattern, located between the first gate pattern and the second gate pattern, for defining a gate electrical connection structure; where the gate electrical connection structure is arranged on the same layer as the first gate and the second gate to electrically connect the first gate and/or the second gate.

Abstract: An integrated circuit includes a set of gates, a first, second and third conductive structure, and a first, second and third via. The set of gates includes a first, second and third gate. The first, second and third conductive structure extend in the first direction and are located on a second level. The first via couples the first conductive structure and the first gate. The second via couples the second conductive structure and the second gate. The third via couples the third conductive structure and the third gate. The first, second and third via are in a right angle configuration. The first and second gate are separated from each other by a first pitch. The first and third gate are separated from each other by a removed gate portion. The first and second conductive structure are separated from each other in the first direction.