Abstract: Presented are mobile charging stations for recharging electrified vehicles, methods for making/using such mobile charging stations, and parking facilities equipped with such mobile charging stations. A mobile charging station includes a frame with drive wheels and a prime mover operable to drive the wheels to propel the charging station. A hydrogen storage container and fuel cell are mounted to the frame. The fuel cell oxidizes hydrogen received from the storage container to generate electrical current. An electrical coupling mechanism connects the fuel cell to a battery pack of an electric-drive vehicle. A resident or remote controller is programmed to receive charge requests to recharge vehicles, and responsively determines path plan data for the mobile charging station. The controller commands the prime mover to propel the mobile charging station from the charger's origin to a charger destination, and enables the fuel cell to transmit electrical current to the vehicle.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: Methods and systems for implementing a traditional computer vision algorithm as a neural network. The method includes: receiving a definition of the traditional computer vision algorithm that identifies a sequence of one or more traditional computer vision algorithm operations; mapping each of the one or more traditional computer vision algorithm operations to a set of one or more neural network primitives that is mathematically equivalent to that traditional computer vision algorithm operation; linking the one or more network primitives mapped to each traditional computer vision algorithm operation according to the sequence to form a neural network representing the traditional computer vision algorithm; and configuring hardware logic capable of implementing a neural network to implement the neural network that represents the traditional computer vision algorithm.

Abstract: Systems, computer-implemented methods, and computer program products to facilitate synthesis of a quantum circuit are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a circuit generation component that generates, iteratively, quantum circuits from 1 to N two-qubit gates, wherein at least one or more iterations (1, 2, . . . , N) adds a single two-qubit gate to circuits from a previous iteration based on using added single 2-qubit gates that represent operations distinct from previous operations relative to previous iterations. The computer executable components can further comprise a circuit identification component that identifies, from the quantum circuits, a desired circuit that matches a quantum circuit representation.

Abstract: A method of forming an integrated circuit includes generating a first and second standard cell layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height different from the first height. The second standard cell layout design is adjacent to the first standard cell layout design. Generating the first standard cell layout design includes generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width. Generating the second standard cell layout design includes generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width different from the first width.

Abstract: Detachable auxiliary power systems are disclosed. In some embodiments, the power system comprises a housing with a cavity, and a detachable portion configured to be received into the cavity. The detachable portion includes a power source such as a rechargeable battery, and may include additional electrical circuits to manage the charge and discharge of the battery. The housing includes a cable for electrically connecting the housing to an external electrical system, such as a vehicle electrical system. When the detachable portion is inserted into the housing, it is electrically connected to the cable, and so able to be charged from the external electrical system, and selectively provide power from the power source to the external electrical system, such as for jump-starting a vehicle.

Abstract: The present application provides an electric protection circuit, which relates to the field of battery power. The electric protection circuit includes a battery pack, a main positive switch, a load device and a main negative switch connected in series. The main positive switch and/or the main negative switch include at least one semiconductor switch. The main positive switch and/or the main negative switch in the electric protection circuit are connected in parallel to a protection module, which absorbs electric energy across two terminals of the main positive switch and/or the main negative switch when the main positive switch and/or the main negative switch are turned off. The technical solution of the present application can improve the safety of the electric protection circuit.

Abstract: An IC structure includes first, second, third, and fourth transistors on a substrate, a first net and a second net. The first net includes a plurality of first metal lines routed on a first metallization layer, and a plurality of first metal vias electrically connecting the plurality of first metal lines to the first and second transistors. The second net includes a plurality of second metal lines routed on a second metallization layer, and a plurality of second metal vias electrically connecting the plurality of second metal lines to the third and fourth transistors. A total length of the second metal lines of the second net is shorter than a total length of the first metal lines of the first net. A count of the f first metal vias of the first net is less than a count of the second metal vias of the second net.

Abstract: In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

Abstract: Systems and methods to semantically compare product configuration models. A method includes receiving a first configuration model and a second configuration model. The method includes generating a first order logic (FOL) representation of the first configuration model and an FOL representation of the second configuration model. The method includes performing a satisfiability modulo theories (SMT) solve for nonequivalence satisfiability on the FOL representation of the first configuration model and the FOL representation of the second configuration model. The method includes storing an indication that the first configuration model is equivalent to the second configuration model when the SMT solve for nonequivalence satisfiability is not satisfied.

Abstract: Systems and methods for chaining data between electric vehicles and electric vehicle stations are disclosed. In an example, an electric vehicle can share a charging profile with a charging station, and the charging station can share collective charging data with the electric vehicle. The collective charging data can include charging profile data electric vehicles which have previously charged at the charging station. Based on the shared data both the electric vehicle and the charging station can perform one or more functions based on the shared data.

Abstract: Techniques regarding topological classification of complex datasets are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a quantum computing component that can encode eigenvalues of a Laplacian matrix into a phase on a quantum state of a quantum circuit. The computer executable components can also comprise a classical computing component that infers a Betti number using a Bayesian learning algorithm by measuring an ancilla state of the quantum circuit.

Abstract: An integrated circuit includes a standard cell including a first output pin and a second output pin configured to each output the same output signal, a first routing path connected to the first output pin, and a second routing path connected to the second output pin. The first routing path includes a first cell group including at least one load cell, the second routing path includes a second cell group including at least one load cell, and the first routing path and the second routing path are electrically disconnected from each other outside the standard cell.

Abstract: A method of manufacturing a semiconductor device includes forming a transistor layer with an M*1st layer that overlays the transistor layer with one or more first conductors that extend in a first direction. Forming an M*2nd layer that overlays the M*1st layer with one or more second conductors which extend in a second direction. Forming a first pin in the M*2nd layer representing an output pin of a cell region. Forming a long axis of the first pin substantially along a selected one of the one or more second conductors. Forming a majority of the total number of pins in the M*1st layer, the forming including: forming second, third, fourth and fifth pins in the M*1st layer representing corresponding input pins of the circuit; and forming long axes of the second to fifth pins substantially along corresponding ones of the one or more first conductors.

Abstract: A system includes a net-identifying module and a false path-eliminating module. The net-identifying module is configured to receive first and second electronic lists associated with a circuit unit, to identify a net of the circuit unit based on the first electronic list, and to provide a net information output that includes information associated with the net. The false path-eliminating module is coupled to the net-identifying module and is configured to select, in the second electronic list, a path of the circuit unit that does not traverse through the net and provide a path information output that includes information associated with the path.

Abstract: Machine learning may include training and drawing inference from artificial neural networks, processes which may include performing convolution and matrix multiplication operations. Convolution and matrix multiplication operations are performed using vectors of block floating-point (BFP) values that may include outliers. BFP format stores floating-point values using a plurality of mantissas of a fixed bit width and a shared exponent. Elements are outliers when they are too large to be represented precisely with the fixed bit width mantissa and shared exponent. Outlier values are split into two mantissas. One mantissa is stored in the vector with non-outliers, while the other mantissa is stored outside the vector. Operations, such as a dot product, may be performed on the vectors in part by combining the in-vector mantissa and exponent of an outlier value with the out-of-vector mantissa and exponent.

Abstract: An neural network (NN) processor includes an input feature map buffer configured to store an input feature matrix, a weight buffer configured to store a weight matrix trained in a form of a, a transform circuit configured to perform a Walsh-Hadamard transform on an input feature vector obtained from the input feature matrix and a weight vector included in the weight matrix to output a transformed input feature vector and a transformed weight vector, and an arithmetic circuit configured to perform an element-wise multiplication (EWM) on the transformed input feature vector and the transformed weight vector.

Abstract: According to an aspect of an embodiment, operations may include obtaining a first matrix associated with an optimization problem associated with a system and obtaining a second matrix associated with the optimization problem. The operations may include obtaining a local field matrix that indicates interactions between the variables of the system as influenced by their respective weights. The operations may include updating the local field matrix. Updating the local field matrix may include performing arithmetic operations with respect to a first portion of the first matrix and a second portion of the second matrix that correspond to a third portion of the local field matrix that corresponds to the one or more variables. The operations may include updating an energy value of the system based on the updated local field matrix and determining a solution to the optimization problem based on the energy value.

Abstract: A computer-implemented method for refining a qubit calibration model is described. The method comprises receiving, at a learning module, training data, wherein the training data comprises a plurality of calibration data sets, wherein each calibration data set is derived from a system comprising one or more qubits, and a plurality of parameter sets, each parameter set comprising extracted parameters obtained using a corresponding calibration data set, wherein extracting the parameters includes fitting a qubit calibration model to the corresponding calibration data set using a fitter algorithm. The method further comprises executing, at the learning module, a supervised machine learning algorithm which processes the training data to learn a perturbation to the qubit calibration model that captures one or more features in the plurality of calibration data sets that are not captured by the qubit calibration model, thereby to provide a refined qubit calibration model.

Abstract: Systems and methods are provided for aggregating and assigning power capacity for charging electric vehicles and providing power to other loads. The systems include a DC bus system used to harmonize and combine power drawn from grid connections having different electrical characteristics such as different voltages or phase levels and from other devices such as energy storage systems and generators at the site. Using the systems and methods can help enable utility customer sites to providing electric vehicle charging, especially for multiple electric vehicles, where the sites would otherwise not have sufficient power to do so without significant and expensive service upgrades and modifications.