Abstract: A method for circuit design based on Artificial Intelligence (AI) and an implementation system thereof. Subcircuits of a circuit-design topology of a historical phase, which are of different categories, are classified and a first feature model are obtained by training; a feature parameter of a circuit is acquired, and finally, the circuit feature parameter is compared with an expected parameter and a corresponding determination result is obtained, thereby a determination is able to be provided for the circuit design, and no simulation is required. As a result, an adjustment on the circuit design or an optimization on the circuit can be performed at a proper time, accordingly, the efficiency in design can be improved.

Abstract: A method and system for guided power grid augmentation determines a minimum resistance path for cells within an integrated circuit (IC) design. The minimum resistance path traces a conducting wire connecting a pin of a cell to an IC tap within the IC design. A voltage drop value for each of the cells is determined so as to identify target cells having a voltage drop value that satisfies a voltage drop criteria. Polygons have defined size characteristics are defined around the minimum resistance paths of the target cells, and conductors, such as additional conductors, are generated within the defined polygons.

Abstract: A computer-implemented method for refining a qubit calibration model is described. The method comprises receiving, at a learning module, training data, wherein the training data comprises a plurality of calibration data sets, wherein each calibration data set is derived from a system comprising one or more qubits, and a plurality of parameter sets, each parameter set comprising extracted parameters obtained using a corresponding calibration data set, wherein extracting the parameters includes fitting a qubit calibration model to the corresponding calibration data set using a fitter algorithm. The method further comprises executing, at the learning module, a supervised machine learning algorithm which processes the training data to learn a perturbation to the qubit calibration model that captures one or more features in the plurality of calibration data sets that are not captured by the qubit calibration model, thereby to provide a refined qubit calibration model.

Abstract: A method includes receiving a design rule deck including a predetermined set of widths and spacings associated with active regions. The method also includes providing a cell library including cells having respective active regions, wherein widths and spacings of the active regions are selected from the predetermined set of the design rule deck. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and a first active region having a first width in the first direction. The second cell has the cell height, and a second active region having a second width in the first direction. The second width is different from the first width. The method further includes manufacturing a semiconductor device according to the design layout.

Abstract: Various embodiments described herein provide for a method and system for relative placement of components for a circuit layout by retrieving a data structure of a first circuit design, the data structure including a location of each component, determining a component characteristic for each component, and selecting a first group of two or more components having a shared component characteristic. Additionally, the method and system can instantiate a second circuit design and retrieve the data structure after the second circuit design is instantiated. The method and system include, for the second circuit design, calculating a first scaling factor and scaling each of the components of the first group from the first circuit design and placing the first group at a location in the second circuit design corresponding to location of the first group within the first circuit design.

Abstract: A die layout calculation method is provided. The method includes: selecting, based on a distribution array of a plurality of dies in a wafer, one die as a reference die; making first movements of a wafer center to determine a first coverage region for each first movement, and determining a feasible region based on a number of complete dies in each first coverage region; making a plurality of second movements of the wafer center in the feasible region to determine a second coverage region for each second movement, and determining a relative position of the wafer center in the reference die corresponding to a maximum number of complete dies in the second coverage region; and determining a die layout comprising a location of each die in the wafer. This method improves the accuracy and efficiency of determining the maximum number of dies.

Abstract: An integrated circuit includes a semiconductor substrate, devices, first tap regions, and second tap regions. The devices are over the semiconductor substrate. The first tap regions are over the semiconductor substrate along a first direction. The second tap regions are over the semiconductor substrate along the first direction. A first pitch between adjacent two of the first tap regions in the first direction is greater than a second pitch between adjacent two of the second tap regions in the first direction.

Abstract: A method of generating a layout diagram for an integrated circuit. The method includes arranging a plurality of cells in the layout diagram. The method further includes placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a routing track of a plurality of routing tracks across a boundary of the first cell and into a second cell of the plurality of cells abutting the first cell.

Abstract: A charging apparatus includes at least one housing including a compartment, an access door connected to the housing and covering the compartment, the access door being movable from an open position to a closed position, a releasable latching mechanism configured to latch the access door in the closed position, a charging terminal in the compartment, a voltage sensing terminal, and a door release circuit coupled to the voltage sensing terminal and to the releasable latching mechanisms and configured to sense a charging voltage applied to the voltage sensing terminal. The door release circuit is configured to selectively unlatch the releasable latching mechanism in response to a voltage within a predetermined voltage range being applied to the voltage sensing terminal.

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

Abstract: A charging network includes one or more charging systems configured to be electrically coupled with a power source. The charging system includes a grid interconnect, a battery energy storage system electrically coupled with the grid interconnect, a charging station electrically coupled with the grid interconnect and the battery energy storage system in parallel, and a computing system. The computing system is configured to determine a requested power load by the charging station at a defined time; determine a defined power value of the grid interconnect; determine one or more charging parameters based at least in part on the requested power load by the charging station at the defined time and the defined power value of the grid interconnect; and generate one or more commands for the battery energy storage system or the charging station to provide a power load based on the one or more charging parameters.

Abstract: An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.

Abstract: A high-voltage portable charging system for remote recharging of an electric vehicle includes a housing, an array of battery cells forming a high-voltage battery disposed in the housing, and a low-voltage battery disposed in the housing. A coupler assembly has a cord and a vehicle connector configured to connect to a vehicle charge port. A switching arrangement is powered by the low-voltage battery and is configured to electrically connect the high-voltage battery to the cord when in a first condition and to de-energize the cord when in a second condition.

Abstract: A system includes a substrate having a first side and a second side opposite the first side, a cell on the substrate having a first pin on either the first side or the second side, and a second pin on the second side, a first signal connected to the first pin, and a second signal connected to the second pin.

Abstract: A method and an electronic device for configuring signal pads between three-dimensional stacked chips are provided. The method includes: obtaining a plurality of frequency response curves corresponding to a plurality of parameter sets; obtaining an operating frequency; selecting a selected frequency response curve from the plurality of frequency response curves according to the operating frequency, where the selected frequency response curve corresponds to a selected parameter set among the plurality of parameter sets; generating, according to the selected parameter set, a signal pad configuration for configuring a first signal pad and a second signal pad on a surface of a chip; and outputting the signal pad configuration.

Abstract: Systems and methods for using an ultrasonic vibration generator to apply vibrational energy to a metal negative electrode of a rechargeable battery. In some examples, the application of vibrational energy to the metal negative electrode occurs during a charging event.

Abstract: Aspects of the invention include systems and methods for implementing a sweepline triangulation technique to optimize spanning graphs for circuit routing. A non-limiting example computer-implemented method includes receiving an unrouted net having a plurality of elements. The elements can include pins, vias, and wires. A sweepline is passed across the unrouted net until the sweepline intersects an element of the plurality of elements. In response to the sweepline intersecting the element, the sweepline is stopped and one or more nodes on the sweepline and one or more previous nodes are identified. A connectivity graph is built from the one or more nodes and the one or more previous nodes. The connectivity graph includes one or more arcs and one or more guides. A minimum spanning tree is built by removing one or more guides from the connectivity graph and the unrouted net is routed based on the minimum spanning tree.

Abstract: An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.

Abstract: A charging control device includes: a determination section configured to make a determination as to whether an auxiliary device battery that supplies electric power to auxiliary devices of a vehicle is within a predetermined first temperature range; and a control section configured to, in a case in which the auxiliary device battery is within the first temperature range, cause a charging section to charge the auxiliary device battery.

Abstract: An example operation includes one or more of retrieving a first amount of energy, by an originating transport, of a minimum amount of energy on a target transport, based on an expended energy by the originating transport to reach a meeting location, provide a needed service, and an estimated expended energy by the originating transport to return to an original location, and retrieving a second amount of energy, by the originating transport, of the minimum amount of energy on the target transport, based on a factor related to providing the service, wherein the factor is greater than the expended energy and the estimated expended energy.