Patents Examined by Nduka Ojeh
  • Patent number: 10208400
    Abstract: A method, for manufacturing a silicon carbide semiconductor device, includes: forming a silicon carbide epitaxial film on a silicon carbide substrate; flattening a surface of the epitaxial film by using chemical mechanical polishing such that the surface of the epitaxial film has an arithmetic mean roughness Ra of 0.3 nm or less; thermally oxidizing the surface of the epitaxial film to form a sacrificial oxide; removing the sacrificial oxide; and cleaning, by using deionized water, a surface of the epitaxial film exposed by the removing of the sacrificial oxide.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: February 19, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Masayuki Miyazaki
  • Patent number: 10204823
    Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 12, 2019
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Stephan A. Cohen, Joel P. de Souza, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana
  • Patent number: 10199587
    Abstract: An organic photoelectric conversion element, an imaging device, and an optical sensor, which can detect a plurality of wavelength regions by a single element structure, are provided. The photoelectric conversion element is formed by providing an organic photoelectric conversion portion including two or more types of organic semiconductor materials having different spectral sensitivities between the first and the second electrodes. Wavelength sensitivity characteristics of the photoelectric conversion element change according to a voltage (bias voltage) applied between the first and the second electrodes. The photoelectric conversion element is mounted in the imaging device and the optical sensor.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: February 5, 2019
    Assignee: SONY CORPORATION
    Inventors: Toru Udaka, Masaki Murata, Rui Morimoto, Osamu Enoki
  • Patent number: 10186556
    Abstract: A thin film transistor array substrate and an organic light emitting diode (OLED) display device including the same are disclosed in which a color layer is disposed on a first substrate corresponding to a white sub-pixel and a non color filter area is included in a second substrate corresponding to the white sub-pixel, and thus, it is possible to lower an amount of reflectance of external light, increase a luminance efficiency, and reduce a power consumption of the OLED display device.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 22, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Howon Choi, Hyesook Kim, MoonBae Gee
  • Patent number: 10186674
    Abstract: A thin-film device includes a resin film which includes a first surface and a second surface facing the first surface, a first inorganic layer on the first surface, a thin-film element on the first inorganic layer, and a second inorganic layer on the second surface, wherein a film density of the second inorganic layer is greater than a film density of the first inorganic layer.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: January 22, 2019
    Assignee: NLT TECHNOLOGIES, LTD.
    Inventors: Kazushige Takechi, Mamoru Okamoto
  • Patent number: 10181464
    Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: January 15, 2019
    Assignee: SOFICS BVBA
    Inventors: Bart Sorgeloos, Benjamin Van Camp, Olivier Marichal
  • Patent number: 10170447
    Abstract: A method and structure for forming a 3D chip stack using a vacuum chuck. The method may include: forming a first bonding layer on a first wafer and first chips, where the first chips are on a first substrate; forming a second bonding layer on a second wafer and second chips, where the second chips are on a second substrate; separating the second chips from the second wafer, wherein a portion of the second bonding layer remains on the second chips; moving the separated second chips to a cleaning chamber using a vacuum chuck; cleaning the separated second chips in the cleaning chamber; and bonding the second bonding layer on the separated second chips to the first bonding layer on the first chips.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wei Lin, Spyridon Skordas
  • Patent number: 10164110
    Abstract: A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: December 25, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 10163679
    Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Siva P. Adusumilli, Steven M. Shank, Richard A. Phelps, Anthony K. Stamper
  • Patent number: 10147805
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure over a semiconductor substrate. The semiconductor device structure also includes a second fin structure over the semiconductor substrate. The second fin structure has a lower height than that of the first fin structure. The second fin structure includes a first sidewall and a second sidewall, and the first sidewall and the second sidewall surround a recess over the second fin structure.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: December 4, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Lung Chen, Kang-Min Kuo, Wen-Hsin Chan
  • Patent number: 10141498
    Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/?10%) and less than or equal to 60 Angstroms (+/?10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/?10%) or 30-50 atomic percent (+/?10%).
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 27, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jon M. Slaughter, Han-Jong Chia
  • Patent number: 10141530
    Abstract: This invention provides a thin film transistor and a manufacturing method thereof, an array substrate, and a display apparatus. This thin film transistor comprises an organic semiconductor layer and a source drain electrode layer, and further comprises a metal oxide insulating layer, wherein the metal oxide insulating layer is provided between the organic semiconductor layer and the source drain electrode layer and has a work function higher than that of the source drain electrode layer. In the thin film transistor provided by this invention, the metal oxide insulating layer having a higher work function can generate an interface dipole barrier so as to reduce the difficulty for the carriers in the source drain electrode to enter the organic semiconductor layer and thereby it is possible to decrease the contact resistance between the source drain electrode layer and the semiconductor layer and improve electrical properties of the thin film transistor.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: November 27, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., SHANGHAI JIAO TONG UNIVERSITY
    Inventors: Wei Huang, Jiaqing Zhao, Wei Tang, Linrun Feng, Xiaojun Guo
  • Patent number: 10141288
    Abstract: Package structures and methods of forming them are described. In an embodiment, a package structure includes an integrated circuit die embedded in an encapsulant and a redistribution structure on the encapsulant. The redistribution structure includes a metallization layer distal from the encapsulant and the integrated circuit die, and a dielectric layer distal from the encapsulant and the integrated circuit die and on the metallization layer. The package structure also includes a first under metallization structure on the dielectric layer and a Surface Mount Device and/or Integrated Passive Device (“SMD/IPD”) attached to the first under metallization structure. The first under metallization structure includes first through fourth extending portions extending through first through fourth openings of the dielectric layer to first through fourth patterns of the metallization layer, respectively.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Hsien Hsieh, Hsien-Wei Chen, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Wei-Cheng Wu
  • Patent number: 10134714
    Abstract: Techniques are disclosed for making a flexible laminated circuit board using a metal conductor onto which a SMD may be attached. Conductive metal strips may be laminated to form a flexible substrate and the metal strips may then be perforated for the placement of LED package leads. The LED packages may be attached to the conductive strips using solder or a conductive epoxy and the upper laminate layer may include perforations exposing portions of the metal strips for the attachment of the LED packages. Alternatively, strings of LED packages may be fabricated by attaching LED packages to conductive strips and these strings may be laminated between flexible sheets to form a laminated LED circuit. Plastic housings may aid in attaching the LED packages to the conductive strips. The plastic housings and/or the laminate sheets may be made of a reflective material.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: November 20, 2018
    Assignee: OSRAM SYLVANIA Inc.
    Inventors: Richard Speer, David Hamby, John Selverian
  • Patent number: 10135028
    Abstract: A flexible display device includes a base substrate defining a display area and a non-display area; a thin film transistor in the display area of the base substrate; an organic light emitting diode on and connected with the thin film transistor; an encapsulation layer on the organic light emitting diode; and a crack preventing portion in the non-display area defined by the base substrate.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: November 20, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: JongSung Kim, JongGeun Yoon, Goeun Jung, HyungGeun Kwon
  • Patent number: 10128359
    Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: November 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Mikio Tsujiuchi, Tetsuya Nitta
  • Patent number: 10121960
    Abstract: A magnetic junction and method for providing the magnetic junction are described. The method includes providing a free layer, providing a pinned layer and providing a nonmagnetic spacer between the free and pinned layers. The free layer is switchable between stable magnetic states using a write current passed through the magnetic junction. At least one of the step of providing the free layer and the step of providing the pinned layer includes depositing a magnetic layer; depositing an adsorber layer on the magnetic layer and performing at least one anneal. The magnetic layer is amorphous as-deposited and includes an interstitial glass-promoting component. The adsorber layer attracts the interstitial glass-promoting component and has a lattice mismatch with the nonmagnetic spacer layer of not more than ten percent. Each of the anneal(s) is at a temperature greater than 300 degrees Celsius and not more than 425 degrees Celsius.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: November 6, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Roman Chepulskyy, Dmytro Apalkov
  • Patent number: 10115924
    Abstract: An OLED apparatus that may include a reflection-anode, a transparent-cathode, and a plurality of stacks between the reflection-anode and the transparent-cathode, wherein, among the plurality of stacks, a thickness of the stack disposed relatively close to the transparent-cathode is larger than a thickness of the stack disposed relatively close to the reflection-anode so that it is possible to optimize a micro-cavity of light emitted from the plurality of stacks, thereby improving a light-emission efficiency and a color reproduction ratio and reducing a color change rate in accordance with a viewing angle.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 30, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Taell Kum, Ki-Woog Song, SoYeon Ahn, Yongjoong Choi, Mingyu Lee
  • Patent number: 10103168
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body which is provided on a substrate and in which an insulating film and an electrode film are alternately stacked. The semiconductor memory device also includes an insulating member which penetrates the stacked body in a stacking direction of the insulating film and the electrode film to thereby separate the stacked body. The semiconductor memory device also includes a semiconductor pillar which penetrates the stacked body in the stacking direction. A maximum portion of the insulating member where a first distance from a side surface of the insulating member to a central plane of the insulating member becomes maximum and a maximum portion of the semiconductor pillar where a second distance from a side surface of the semiconductor pillar to a center line of the semiconductor pillar becomes maximum being provided in different positions in the stacking direction.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: October 16, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Kotaro Noda
  • Patent number: 10079352
    Abstract: Embodiments of the present disclosure provide a manufacturing method for a flexible device and a flexible display device. The manufacturing method for a flexible device comprises: step S1, forming an organosiloxane layer on a supporting substrate; step S2, forming a flexible substrate on the organosiloxane layer; step S3, forming a display device on the flexible substrate; step S4, performing an oxidation treatment on a surface of the organosiloxane layer that contacts the supporting substrate such that a silicon dioxide layer is formed between the organosiloxane layer and the supporting substrate; and step S5, peeling off the supporting substrate from the silicon dioxide layer.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: September 18, 2018
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Leilei Cheng, Yuankui Ding, Dongfang Wang, Ce Zhao