Abstract: Various structures having a fuse and methods for forming those structures are described. An embodiment is a method. The method comprises attaching a first die to a first side of a component using first electrical connectors. After the attaching, at least one of (i) the first die comprises a first fuse, (ii) the first side of the component comprises a second fuse, (iii) a second side of the component comprises a third fuse, the second side being opposite the first side, or (iv) a combination thereof. The method further comprises after the attaching the first die to the first side of the component, blowing the first fuse, the second fuse, the third fuse, or a combination thereof.

Abstract: A barrier film configured to reduce degradation of an organic EL element includes a first inorganic film, a second inorganic film, and a third inorganic film which are provided in order from a base substrate, a first organic film between the first inorganic film and the second inorganic film, and a second organic film between the second inorganic film and the third inorganic film. The first organic film has a plurality of first through holes formed therein so that the first inorganic film is in contact with the second inorganic film through the first through holes. The second organic film has a plurality of second through holes formed therein so that the second inorganic film is in contact with the third inorganic film through the second through holes.

Abstract: A TFT-driven display device includes an upper substrate and a lower substrate facing each other, multiple TFTs disposed on a side of the lower substrate facing the upper substrate, and a metal layer disposed on a side of the upper substrate facing the lower substrate. The metal layer includes multiple horizontal metal wirings extending in a direction of scanning lines and including portions overlapping with an active layer of the TFTs in the light transmission direction, the overlapping portions have a pattern width less than that of other portions that do not overlap with the active layer. A photo-leakage current caused by light reflected by the metal layer may be reduced, because no portion of the metal layer is provided in the position opposed to the active layer of the TFTs located on a TFT array substrate.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate including an emission area, a sensor area, and an opening area. The display also includes an OLED formed in the emission area of the substrate, wherein the OLED includes an organic light emitting layer interposed between pixel and opposite electrodes, wherein the opposite electrode is configured to firstly reflect light emitted from the intermediate layer. The display further includes a photo sensor formed in the sensor area of the substrate and a partition wall located adjacent to the photo sensor and at least partially surrounding the photo sensor. The partition wall is configured to secondly reflect at least a portion of the first reflected light, and wherein the photo sensor is configured to at least partially absorb the second reflected light.

Abstract: The present invention provides electrostatic discharge protectors. One aspect of the present invention provides an electrostatic discharge protector includes a substrate, an electrostatic discharge protection circuit disposed on the substrate, and a pickup ring surrounding the electrostatic discharge protection circuit. The pickup ring has a plurality of low resistance zones where a doping layer, a contact and a metal layer are connected in sequence, and the low resistance zones are distributed within the pickup ring separately and unequally.

Abstract: Provided is an organic electroluminescent device including, in an order mentioned: a reflective electrode; an organic electroluminescent layer; a light extraction layer; and a transparent substrate, wherein a ratio (w/d) is 9 or more where “d” denotes a total average thickness from the organic electroluminescent layer to the transparent substrate and “w” denotes a minimum width of a non-light-emitting region present outside of an outer periphery of an effective light-emitting region in the organic electroluminescent layer.

Abstract: A donor mask and a method of manufacturing an organic light-emitting display apparatus by using the donor mask. The method includes transferring a portion corresponding to a through hole of a transferring layer deposited on a light-to-heat conversion layer of the donor mask onto at least a portion of pixel electrodes on a substrate.

Abstract: A diode comprising a reduced surface field effect trench structure, the reduced surface field effect trench structure comprising at least two trenches formed in a substrate and separated from one another by a joining region of the substrate, the joining region comprising an electrical contact and a layer of p-doped semiconductor material.

Abstract: In an organic EL display device, a resistance of a cathode electrode of OLEDs is substantially reduced while maintaining a higher opening ratio of pixels as an entire display area. A reference power supply line is formed on a glass substrate, and receives a reference potential for driving the OLED. The OLED is formed on the glass substrate where the reference power supply line is formed, and has a structure in which a lower electrode, an organic material layer, and an upper electrode that is a cathode electrode common to plural pixels are laminated on each other in the order from the bottom. In some of the plural pixels, a cathode contact that penetrates through the organic material layer, and electrically connects the upper electrode to the reference power supply line is formed within an opening area corresponding to a W sub-pixel.

Abstract: There is provided an organic electroluminescent element including a plurality of light-emitting units including at least a first light-emitting unit containing at least a first light-emitting layer, and a second light-emitting unit containing at least a second light-emitting layer, and a charge generating layer disposed between the first light-emitting unit and the second light-emitting unit. The first light-emitting unit is disposed between an anode and a cathode. The second light-emitting unit is disposed between the first light-emitting unit and the cathode. A film thickness of a hole transport layer in the second light-emitting unit is not less than 10% and not more than 25% to a total film thickness of the second light-emitting unit.

Abstract: A semiconductor device connected by an anisotropic conductive film including a first insulation layer, a conductive layer, and a second insulation layer one above another, wherein the conductive layer has an expansion length of 20% or less in a width direction thereof, and the second insulation layer has an expansion length of 50% or more in a width direction thereof, the expansion length is calculated according to Equation 1, below, after glass substrates are placed on upper and lower sides of the anisotropic conductive film respectively, followed by compression at 110° C. to 200° C. for 3 to 7 seconds under a load of 1 MPa to 7 MPa per unit area of a sample, Increased ratio of expansion length (%)=[(length of corresponding layer in width direction after compression?length of corresponding layer in width direction before compression)/length of corresponding layer in width direction before compression]×100.

Abstract: An electronic package includes a leadframe and a plurality of pins. The electronic package also includes a first gallium nitride (GaN) transistor comprising a source, gate, and drain and a second GaN transistor comprising a source, gate, and drain. The source of the first GaN transistor is electrically connected to the leadframe and the drain of the second GaN transistor is electrically connected to the leadframe. The electronic package further includes a first GaN diode comprising an anode and cathode and a second GaN diode comprising an anode and cathode. The anode of the first GaN diode is electrically connected to the leadframe and the anode of the second GaN diode is electrically connected to the leadframe.

Abstract: A semiconductor power device is provided, comprising a substrate of a first conductive type, a buffering layer of a second conductive type formed on the substrate, a voltage supporting layer formed on the buffering layer, and alternating sections of different conductive types formed at the substrate. The voltage supporting layer comprises first semiconductor regions of the first conductive type and second semiconductor regions of the second conductive type, wherein the first semiconductor regions and the second semiconductor regions are alternately arranged. The alternating section and the buffering layer form a segmented structure of alternated conductive types, which is used as an anode of the semiconductor device.

Abstract: An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins.

Abstract: Provided are resistive random access memory (ReRAM) cells and methods of fabricating thereof. The ReRAM cells may include a first layer operable as a bottom electrode. The ReRAM cells may also include a second layer operable as a variable resistance layer configured to switch between at least a first resistive state and a second resistive state. The ReRAM cells may further include a third layer formed over the second layer. The third layer may have a substantially constant electrical resistivity. Moreover, the third layer may include a ternary metal-silicon nitride having a ratio of metal to silicon that is between about 1:1 and 1:4. Furthermore, the ternary metal-silicon nitride may include a metal that has an atomic weight that is greater than 90. The ReRAM cells may further include a fourth layer operable as a top electrode.

Abstract: To connect multiple LED devices, each LED device is placed in a holder. A first wire is connected to a first wire connection point on the holder and a second wire is connected to a second wire connection point on the holder. The first wire is also connected to a first wire connection point on a circuit board The second wire is also connected to a second wire connection point on the circuit board. A connector may be used to connect the wires to the wire connection points on the circuit board. The circuit board includes traces to connect the LED devices to each other or to other components.

Abstract: A method of forming a semiconductor structure includes forming a first plurality of fins in a first region of a semiconductor substrate and a second plurality of fins in a second region of a semiconductor substrate. A gate structure is formed covering a first portion of the first and second plurality of fins. The gate structure does not cover a second portion of the first and second plurality of fins. A first epitaxial layer is grown surrounding the second portion of the first plurality of fins and a second epitaxial layer is grown surrounding the second portion of the second plurality of fins. An ILD layer is deposited and partially etched to expose the first epitaxial layer and a top portion of the second epitaxial layer. A metal layer is deposited around the first epitaxial layer and above the top portion of the second epitaxial layer.

Abstract: An opto-electronic circuit board includes a substrate, a cavity, blind vias, metal layers, a first chip, a second chip, and the optical component. The substrate includes a first circuit layer, a second circuit layer, and a dielectric layer disposed between the first circuit layer and the second circuit layer. The cavity is disposed on the dielectric layer, in which the cavity extends from the first circuit layer to the second circuit layer. The blind vias are disposed at opposite sides of the cavity. The first chip is disposed on the second circuit layer with corresponding to one of the blind vias. The second chip is disposed on the second circuit layer with corresponding to the other one of the blind vias. The optical component is disposed in the cavity, in which the second surface of the optical component is connected to the first circuit layer.

Abstract: A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present.