Patents Examined by Nduka Ojeh
  • Patent number: 10056382
    Abstract: A method of forming an improved field-effect transistor device is provided. The method includes forming a tensile stressor near a first semiconductor fin. The first semiconductor fin is a fin of an n-channel field-effect transistor. The n-channel field-effect transistor is formed on a substrate. The method also includes forming a compressive stressor near a second semiconductor fin. The second semiconductor fin is a fin of a p-channel field effect transistor. The p-channel field-effect transistor is formed on the substrate. The method can also include forming neutral material over the at least one n-channel and p-channel field effect transistor. The method can also include achieving different device performance by configuring a stressor distance to fin and/or by configuring a stressor volume.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 21, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dechao Guo, Juntao Li, Sanjay C. Mehta, Robert R. Robison, Huimei Zhou
  • Patent number: 10050050
    Abstract: A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Harry Hak-Lay Chuang, Wei-Cheng Wu, Ya-Chen Kao
  • Patent number: 10037919
    Abstract: A structure and method of making a semiconductor device includes a single-gated vertical field effect transistor (VFET), that has a first fin on a first bottom source/drain region, a gate of a first work force metal (WFM) surrounding the first fin, and a single gate contact connected to the first WFM. Also included is a double-gated VFET, that has a second fin on a second bottom source/drain region, a first gate of the first WFM disposed on a first side of the second fin, a second wider gate of a second WFM disposed on a second side of the second fin, a first gate contact contacting the first narrow gate, and a second gate contact contacting the second wider gate of the second WFM on the second side.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 31, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruilong Xie, Chun-Chen Yeh, Kangguo Cheng, Tenko Yamashita
  • Patent number: 10033017
    Abstract: An organic light emitting display device has a display region and a first peripheral region surrounding at least one side of the display region. The organic light emitting display device includes a first substrate a first substrate, a plurality of pixels on the first substrate, the plurality of pixels being included in the display region, at least one of the plurality of pixels including an organic light emitting element, and a driving circuit on the first substrate and in the first peripheral region. At least one of the pixels includes a first transmission portion and at least one light emitting portion, and the first peripheral region includes at least one second transmission portion.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: July 24, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dong-Gyu Kim
  • Patent number: 10032854
    Abstract: A semiconductor integrated circuit device may include a cell capacitor connected with any one of a first electrode and a second electrode of an access device. The cell capacitor may include a first cell cap array and a second cell cap array separated from the first cell cap array. A voltage terminal for driving the cell capacitor may be connected to a connection node between the first cell cap array and the second cell cap array.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: July 24, 2018
    Assignee: SK hynix Inc.
    Inventors: Jong Su Kim, Dong Kun Lee
  • Patent number: 10026926
    Abstract: Embodiments relate to a method of forming an organic light emitting diode (OLED) display device. A first inorganic layer, a first organic layer, and a second inorganic layer are formed on pixel regions of an OLED display device. At least part of a first inorganic layer is formed using atomic layer deposition (ALD), such that the first inorganic layer completely covers particles generated on the OLED. Embodiments also relate to an OLED display device with pixel regions, each pixel region including an OLED, a bank layer across a boundary between adjacent pixel regions, and a first inorganic layer on at least a portion of the OLED and the bank layer. The first inorganic layer includes a first inorganic sub-layer and a second inorganic sub-layer.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: July 17, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Young Lee, Ji-Min Kim, Gi-Youn Kim, Sang-Hoon Oh
  • Patent number: 9997589
    Abstract: A display device according to the invention includes: a first substrate that includes a flexible substrate, is segmented into a display area and a non-display area outside the display area, and includes a thin film transistor and an electroluminescent light-emitting element formed on the display area of the flexible substrate; and an IC chip that is bonded on the non-display area of the first substrate via an anisotropic conductive film, wherein the first substrate includes, between the flexible substrate and the anisotropic conductive film, at least one or more support layers whose plan view shape is larger than that of the IC chip and whose hardness is higher than that of the flexible substrate, and the IC chip is located inside the at least one or more support layers in a plan view.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: June 12, 2018
    Assignee: Japan Display Inc.
    Inventor: Kazuto Tsuruoka
  • Patent number: 9991465
    Abstract: A display device includes: a lower substrate comprising an active area, and a peripheral area outside the active area; a thin film transistor layer on the lower substrate; a plurality of pixel electrodes on the thin film transistor layer and in the active area; an encapsulating portion on the pixel electrode and encapsulating the pixel electrode; and a pattern layer comprising a plurality of patterns on the encapsulating portion, wherein the encapsulating portion covers a first area of the lower substrate and exposes a second area outside the first area, and the pattern layer comprises a crack preventing portion at the peripheral area.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: June 5, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hee Chul Jeon
  • Patent number: 9985208
    Abstract: A method for manufacturing a display device, includes preparing a display panel including a base substrate, an encapsulation layer facing the base substrate, and an organic light emitting device formed between one surface of the base substrate and the encapsulation layer, attaching a support layer to the other surface of the base substrate through an adhesive layer, curing the adhesive layer through irradiation of UV light, and mounting a driving chip on one surface of the display panel. The adhesive layer includes an acryl-based compound, a UV curable compound, and a photoinitiator.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: May 29, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyeon Deuk Hwang, Su Kyoung Kim, So Yeon Joo
  • Patent number: 9985094
    Abstract: A super junction includes a substrate and an epitaxial layer over the substrate, the epitaxial layer having a first dopant type. The super junction further includes an angled trench in the epitaxial layer, the angled trench having sidewalls disposed at an angle ranging from about 85-degrees to about 89-degrees with respect to a top surface of the epitaxial layer. The super junction further includes a doped body in the epitaxial layer surrounding the angled trench, the doped body having a second dopant type, the second dopant type opposite that of the first dopant type.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 29, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jheng-Sheng You, Che-Yi Lin, Shen-Ping Wang, Lieh-Chuan Chen, Chih-Heng Shen, Po-Tao Chu
  • Patent number: 9960219
    Abstract: An organic light emitting display device includes a substrate; an anode electrode on the substrate; an auxiliary electrode on the substrate in a same layer as the anode electrode; a partition supporter on the auxiliary electrode; a partition on the partition supporter; an organic emitting layer on the anode electrode and on the partition such that portions separated on the partition are separated from other portions; and a cathode electrode connected with the organic emitting layer and the auxiliary electrode. A lower surface of the partition supporter includes a pair of short sides; and a pair of long sides connecting the pair of short sides and including at least one inclined surface.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: May 1, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: JaeSung Lee, Jonghyeok Im
  • Patent number: 9935278
    Abstract: A display apparatus including a display panel, a buffer, and a curved buffer. The display panel includes a curved portion connected to a flat portion. The buffer overlaps the flat portion and having a first thickness. The curved buffer is on a same layer as the buffer and overlaps the curved portion, the curved buffer having a second thickness greater than the first thickness.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: April 3, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minseop Kim, Won-il Lee, Younhwan Jung
  • Patent number: 9922866
    Abstract: A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an n+ silicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Stephan A. Cohen, Joel P. de Souza, Karen A. Nummy, Daniel J. Poindexter, Devendra K. Sadana
  • Patent number: 9905420
    Abstract: Methods of forming silicon germanium tin (SixGe1-xSny) films are disclosed. Exemplary methods include growing films including silicon, germanium and tin in an epitaxial chemical vapor deposition reactor. Exemplary methods are suitable for high volume manufacturing. Also disclosed are structures and devices including silicon germanium tin films.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: February 27, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Joe Margetis, John Tolle
  • Patent number: 9900102
    Abstract: Embodiments of the present disclosure provide an apparatus comprising an integrated circuit with a chip-on-chip and chip-on-substrate configuration. In one instance, the apparatus may include an optical transceiver with an opto-electronic component disposed in a first portion of a die, and a trace coupled with the opto-electronic component and disposed to extend to a surface in a second portion of the die adjacent to the first portion, to provide electrical connection for the integrated circuit and another integrated circuit to be coupled with the second portion of the die in a chip-on-chip configuration. The apparatus may include a second trace disposed in the second portion of the die to extend to the surface in the second portion, to provide electrical connection for the other integrated circuit and a substrate to be coupled with the second portion of the die in a chip-on-substrate configuration. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: February 20, 2018
    Assignee: Intel Corporation
    Inventors: Olufemi I. Dosunmu, Myung Jin Yim, Ansheng Liu
  • Patent number: 9893133
    Abstract: An organic light emitting diode (OLED) display includes a substrate including a penetrated portion positioned in a display area for displaying an image and a light emission region neighboring the penetrated portion. The OLED display also includes an OLED positioned on the light emission region of the substrate.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: February 13, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gyung Soon Park, Il Gon Kim
  • Patent number: 9887259
    Abstract: A semiconductor device—e.g., a super junction power MOSFET—includes a number of columns of one type of dopant formed in a region of another type of dopant. Generally speaking, the columns are modulated in some manner. For example, the widths (e.g., diameters) of some columns are greater than the widths of other columns.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: February 6, 2018
    Assignee: Vishay-Siliconix
    Inventors: Deva Pattanayak, Olof Tornblad
  • Patent number: 9887381
    Abstract: Provided are an organic light-emitting display device and method of manufacturing the same. An organic light-emitting display device includes: an organic light-emitting unit between two substrates, and an adhesive unit configured to fix the two substrates, the adhesive unit including: a plurality of additives, and at least two regions configured to: suppress infiltration of external moisture into the organic light-emitting unit, and decrease separation of at least one of the two substrates from the adhesive unit caused by the external moisture, and wherein the at least two regions have respective concentrations of the plurality of additives different from each other.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: February 6, 2018
    Assignee: LG Display Co., Ltd.
    Inventor: YoungHoon Shin
  • Patent number: 9882163
    Abstract: A display device is disclosed. In one aspect, the device includes first and second substrates each including a display area and a non-display area around the display area, a plurality of pixels formed in the display area of the first substrate and an internal circuit unit formed in the non-display area of the first substrate and electrically connected to the pixels. The device further includes a sealing member formed between the non-display areas of the first and second substrates to surround the display areas. The sealing member includes a first portion and a second portion, the second portion surrounded by the first portion and at least partially overlapping the internal circuit unit, and a groove is formed in the second substrate at a position corresponding to the second portion of the sealing member.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: January 30, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Cheondeok Park
  • Patent number: 9875998
    Abstract: Fabricating an optics wafer includes providing a wafer comprising a core region composed of a glass-reinforced epoxy, the wafer further comprising a first resin layer on a top surface of the core region and a second resin layer on a bottom surface of the core region. The wafer further includes vertical transparent regions that's extend through the core region and the first and second resin layers. The wafer is thinned from its top surface and its bottom surface so that a resulting thickness is within a predetermined range without causing glass fibers of the core region to become exposed. Optical structures ate provided on one or more exposed surfaces of at least some of the transparent regions.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: January 23, 2018
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventor: Hartmut Rudmann