Abstract: A semiconductor device includes a substrate extending in a first direction to define a substrate length and a second direction perpendicular to the first direction to define a substrate width. A first semiconductor fin is formed on an upper surface of the substrate. The first semiconductor fin extends along the second direction at a first distance to define a first fin width. A second semiconductor fin is formed on the upper surface of the substrate. The second semiconductor fin extends along the second direction at a second distance to define a second fin width. The second distance may be different with respect to the first distance such that the first and second fin widths are different with respect to one another.

Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.

Abstract: In an organic EL display device, a resistance of a cathode electrode of OLEDs is substantially reduced while maintaining a higher opening ratio of pixels as an entire display area. A reference power supply line is formed on a glass substrate, and receives a reference potential for driving the OLED. The OLED is formed on the glass substrate where the reference power supply line is formed, and has a structure in which a lower electrode, an organic material layer, and an upper electrode that is a cathode electrode common to plural pixels are laminated on each other in the order from the bottom. In some of the plural pixels, a cathode contact that penetrates through the organic material layer, and electrically connects the upper electrode to the reference power supply line is formed within an opening area corresponding to a W sub-pixel.

Abstract: A chip package includes an integrated circuit and an optical integrated circuit (such as a hybrid integrated circuit) with an optical source and/or an optical receiver. The integrated circuit and the optical integrated circuit may be proximate to each other on opposite sides of an interposer in the chip package. Moreover, the integrated circuit may include a driver circuit of electrical signals for the optical source and/or a receiver circuit of electrical signals from the optical receiver. Furthermore, the optical integrated circuit may be positioned in a hole or an etch pit in a substrate, and an alignment feature may mechanically couple the substrate to an optical-fiber assembly, so that the optical-fiber assembly is positioned relative to the interposer and the optical integrated circuit. In particular, the optical-fiber assembly may partially overlap the interposer, so that optical signals are provided and/or received from the optical integrated circuit through the interposer.

Abstract: Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region.

Abstract: A display device according to the invention includes: a first substrate that includes a flexible substrate, is segmented into a display area and a non-display area outside the display area, and includes a thin film transistor and an electroluminescent light-emitting element formed on the display area of the flexible substrate; and an IC chip that is bonded on the non-display area of the first substrate via an anisotropic conductive film, wherein the first substrate includes, between the flexible substrate and the anisotropic conductive film, at least one or more support layers whose plan view shape is larger than that of the IC chip and whose hardness is higher than that of the flexible substrate, and the IC chip is located inside the at least one or more support layers in a plan view.

Abstract: An array substrate, a manufacture method thereof, and a display device with the array substrate are provided. The array substrate includes a substrate; a first gate scanning line; a first gate insulating layer; an active layer; a date scanning line; a pixel electrode formed in a pixel unit defined by the first gate scanning line and the data scanning line and over the data scanning line; and a second gate scanning line formed over or below the first gate scanning line. The second gate scanning line is substantially overlapped with the first gate scanning line in a stacking direction of the array substrate, and is arranged to be insulated from the first gate scanning line, the active layer, the data scanning line, and the pixel electrode, respectively.

Abstract: Fabricating an optics wafer includes providing a wafer including a core region composed of a glass-reinforced epoxy. The wafer further includes a first resin layer on a top surface of the core region and a second resin layer on a bottom surface of the core region. The core region and first and second resin layers are substantially non-transparent for a specific range of the electromagnetic spectrum. The wafer further includes vertical transparent regions that extend through the core region and the first and second resin layers and are composed of a solid material that is substantially transparent for the specific range of the electromagnetic spectrum. The wafer is thinned, and optical structures are provided on one or more exposed surfaces of at least some of the transparent regions.

Abstract: A light-emitting device includes a photoluminescent layer that emits light containing first light, a light-transmissive layer located on or near the photoluminescent layer, a low-refractive-index layer and a high-refractive-index layer. A submicron structure is defined on the photoluminescent layer and/or the light-transmissive layer. The low-refractive-index layer is located on or near the photoluminescent layer so that the photoluminescent layer is located between the low-refractive-index layer and light-transmissive layer. The high-refractive-index layer is located on or near the low-refractive-index layer so that the low-refractive-index layer is located between the high-refractive-index layer and the photoluminescent layer.

Abstract: An interconnect structure includes a first dielectric material having an undercut region located at an upper surface thereof. A first conductive structure is located above a first area of the undercut region. The first conductive structure comprises a first conductive metal portion having a diffusion barrier portion located on one sidewall surface of the first conductive metal portion and having a metal liner located on another sidewall surface and a bottom surface of the first conductive metal portion. A second conductive structure is located above a second area of the undercut region. The second conductive structure comprises a second conductive material portion having a diffusion barrier portion located on one sidewall surface of the second conductive material portion and having a metal liner located on another sidewall surface and a bottom surface of the second conductive metal portion. A gap is located between the first and second conductive structures.

Abstract: In general, according to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a memory film, a partitioning member, a first interlayer insulating film, and a first plug. The stacked body is provided on the substrate, and including a plurality of electrode films and a plurality of insulating films. The semiconductor pillar is provided in the stacked body. The partitioning member is provided in the stacked body. The first plug is connected to the semiconductor pillar. A central axis of the first plug is shifted from a central axis of the semiconductor pillar so as to approach the nearest partitioning member.

Abstract: Provided is a semiconductor device that can suppress a temperature increase in beam leads while reducing the number of wiring lines and can suppress an increase in manufacturing costs. The semiconductor device is provided with a power module including an upper arm and a lower arm each configured by connecting in parallel a plurality of power elements and a plurality of rectifying elements. Current to one arm flows through a plurality of separately wired beam leads. A portion of the power elements and a portion of the rectifying elements in one arm form a pair and are connected by a common beam lead.

Abstract: A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor.

Abstract: An organic EL display device includes a first organic layer that is arranged between lower electrodes and an upper electrode, and formed of a plurality of layers including a light emitting layer, a laminated auxiliary line that has a first auxiliary line and a second auxiliary line, and laminated on each other in order, and extend in one direction between two of pixels adjoining each other, and a second organic layer that is formed of a plurality of the same layers as the first organic layer, and arranged in contact with the first auxiliary line in a connection hole opened in the second auxiliary line so as to come out of contact with the first organic layer, in which the upper electrode is arranged in contact with the first auxiliary line around the second organic layer so as to embed the connection hole.

Abstract: A semiconductor device in which short circuit capability can be improved while decline in overall current capability is suppressed. In the semiconductor device, a plurality of IGBTs (insulated gate bipolar transistors) arranged in a row in one direction over the main surface of a semiconductor substrate include an IGBT located at an extreme end in the one direction and an IGBT located more centrally than the IGBT located at the extreme end. The current capability of the IGBT located at the extreme end is higher than the current capability of the IGBT located centrally.

Abstract: The present invention relates to an organic electroluminescence element in which a transparent first electrode, an organic light emitting layer, a second electrode are stacked on a translucent substrate in this order. The translucent substrate includes a moisture-proof layer facing the first electrode. An LR layer and an HR layer having a refractive index higher than a refractive index of the LR layer are situated between the moisture-proof layer and the first electrode in this order from the moisture-proof layer. An uneven structure is provided at an interface between the LR layer and the HR layer. A linear expansivity ? of the moisture-proof layer, and a linear expansivity ? of the LR layer, and a linear expansivity ? of the HR layer satisfy a relation of ?????.

Abstract: A thin film transistor based on carbon nanotubes comprises a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconductor layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconductor layer by the insulating layer. The semiconductor layer includes a number of semiconductor fragments, each of the number of semiconductor fragments includes multilayer semiconductor molecular layers, and a quantity of layers of the number of semiconductor molecular layers ranges from about 1 to about 20.

Abstract: A semiconductor device with a strained region is provided. The semiconductor device includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the second dielectric layer having a first fin disposed therein and an interface disposed proximate the first fin. The interface includes a first oxide region disposed in the first dielectric layer and a second oxide region disposed in the second dielectric layer. The interface induces strain in a region of the semiconductor device. A method of making a semiconductor device with a strained region is also provided.

Abstract: A semiconductor device includes a semiconductor mesa which is formed between cell trench structures extending from a first surface into a semiconductor body. The semiconductor mesa includes a body zone forming a first pn junction with a drift zone between the body zone and a second surface opposite to the first surface. Source zones are arranged along a longitudinal axis of the semiconductor mesa at a first distance from each other and form second pn junctions with the body zone. A barrier structure, which has the conductivity type of the source zones, forms at least one of a unipolar homojunction with the drift zone and a pn junction with the body zone at least outside a vertical projection of the source zones perpendicular to the first surface. The barrier structure may be absent in the vertical projection of the source zones.

Abstract: Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment.