Patents Examined by Neel D Shah
  • Patent number: 11668745
    Abstract: A probe apparatus and a wafer inspection method are provided. The probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe, and a processing unit in communication with the tester and configured to move the tester circumferentially around the wafer such that the probe is moved from a first portion on the wafer to a second portion on the wafer.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: June 6, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Yi-Ju Chen, Jui-Hsiu Jao
  • Patent number: 11662367
    Abstract: An inspection apparatus includes: a probe card having a probe to be in contact with an object to be inspected; an upper module having a mounting portion on which the object to be inspected is mounted; a movement mechanism that is configured to support the upper module to be liftable and lowerable and that is able to move the upper module in a horizontal direction; and a lifting and lowering mechanism that is provided under the movement mechanism and that is able to push up the upper module toward the probe card, wherein an axis passing through a point of action of a pushing force when the lifting and lowering mechanism pushes up the upper module and an axis passing through a point of action of a load received by the probe card are arranged at positions to be common.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: May 30, 2023
    Assignee: Tokyo Electron Limited
    Inventor: Masahito Kobayashi
  • Patent number: 11655792
    Abstract: The present disclosure relates to voltage sensing mechanisms. One example embodiment includes a voltage-measurement device. The voltage-measurement device includes a housing. The voltage-measurement device also includes an extendible gripper configured to be removably attached to a wire under test. Additionally, the voltage-measurement device includes at least one power supply. Further, the voltage-measurement device includes a power management chip electrically coupled to the at least one power supply and configured to manage a range of input voltages from the at least one power supply. The power management chip comprises a synchronous boost voltage regulator. Additionally, the voltage-management device has a microprocessor electrically coupled to the power management chip and the extendible gripper. The microprocessor is configured to receive electrical power from the power management chip.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: May 23, 2023
    Assignee: Trillium Worldwide, Inc.
    Inventor: Ai Wei Zhou
  • Patent number: 11656267
    Abstract: A method of characterizing a field-effect transistor, including: a step of application, to the transistor gate, of a single voltage ramp; and a step of interpretation both of gate capacitance variations and of drain current variations of the transistor.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: May 23, 2023
    Assignee: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Abygael Viey, William Vandendaele, Jacques Cluzel, Jean Coignus
  • Patent number: 11651910
    Abstract: An example polarity inverter includes multiple contactors, each of which includes switches that are controllable to configure a current path. Each of the multiple contactors includes contacts, which are interleaved such that first contacts to receive voltage having a first polarity alternate with second contacts to receive voltage having a second polarity, where the first polarity and the second polarity are different. The polarity inverter also includes a first conductive plate to connect electrically to each of the first contacts, and a second conductive plate to connect electrically to each of the second contacts. The first conductive plate and the second conductive plate are in parallel. A dielectric material is between the first conductive plate and the second conductive plate.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: May 16, 2023
    Assignee: TERADYNE, INC.
    Inventors: Frank Parrish, Diwakar Saxena, Michael Herzog, Edward Patrick Dague
  • Patent number: 11644558
    Abstract: The invention relates to a distance-measuring device for determining a distance between a reflection body in a conducting structure and a coupling region for electromagnetic waves, which region is provided on an end section of the conducting structure, said measuring device comprising a transmitting and receiving device, and a conduction junction (1) provided on the coupling region, for coupling the transmitting and receiving device to the conducting structure containing a medium, in order to couple an electromagnetic wave into the conducting structure, and to decouple the electromagnetic wave, reflected on the reflection body, from the conducting structure. Said measuring device also comprises an evaluation device for determining the distance between the coupling region and the reflection body from the complex reflection coefficient between the coupled electromagnetic wave and the decoupled electromagnetic wave. The invention also relates to the corresponding method.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: May 9, 2023
    Assignee: Astyx MPS GmbH
    Inventors: Andre Giere, Sebastian Lüttich
  • Patent number: 11640775
    Abstract: A display device including a substrate having a display area and a non-display area outside the display area, a plurality of pixels disposed on the substrate in the display area, an external circuit bonded on the substrate in the non-display area, a first signal line disposed on the substrate in the non-display area and surrounding at least a portion of the display area, the first signal line being electrically connected to the external circuit, and a second signal line disposed in the non-display area and surrounding at least a portion of the first signal line, the second signal line being electrically connected to the external circuits.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: May 2, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Haegoo Jung
  • Patent number: 11630129
    Abstract: Disclosed is a probe card for testing a wafer. The probe card includes a substrate and a block including an insulation portion and a conducting portion disposed on the insulation portion. Here, the insulation portion includes a via and a probe pin which comes into contact with an object to be tested. The conducting portion includes a contact point electrically connected to the substrate and a conducting pattern passing through the via and electrically connecting the contact point to the probe pin. A pitch between a plurality of such probe pins is smaller than a pitch between a plurality of such contact points. The block includes a plurality of unit blocks. The plurality of unit blocks each include the insulation portion and the conducting portion, and at least parts of the insulation portions of the unit blocks are arranged while being spaced apart from each other.
    Type: Grant
    Filed: October 19, 2021
    Date of Patent: April 18, 2023
    Assignee: PRO-2000 Co., LTD
    Inventor: Jun Soo Cho
  • Patent number: 11630132
    Abstract: A Fast Faraday Cup includes a group of electrodes including a grounded electrode having a through hole and a collector electrode configured with a blind hole that functions a collector hole. The electrodes are configured to allow a beam (e.g., a non-relativistic beam) to fall onto the grounded electrode so that the through hole cuts a beamlet that flies into the collector hole and facilitates measurement of the longitudinal distribution of particle charge density in the beam. The diameters, depths, spacing and alignment of the collector hole and the through hole are controllable to enable the Fast Faraday day cup to operate with a fast response time (e.g., fine time resolution) and capture secondary particles.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 18, 2023
    Assignee: FERMI RESEARCH ALLIANCE, LLC
    Inventors: Ding Sun, Alexander Shemyakin
  • Patent number: 11624759
    Abstract: A testing socket includes a metal block, an assembly block, an analog ground probe pin and a digital ground probe pin. The metal block is formed with a concave portion and used to connect to an independent main ground. The assembly block is electrically isolated from the metal block, and detachably embedded in the recess, so that the metal block and the assembly block are assembled together to be a probe holder. The digital grounding probe is inserted in the metal block, electrically connected to the independent main ground through the metal block. The digital ground probe pin can be electrically connected to a device to be tested (DUT) and the independent main ground. The analog ground probe pin is inserted in the assembly block, and electrically connected to the DUT and another independent main ground.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: April 11, 2023
    Assignees: GLOBAL UNICHIP CORPORATION, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Chieh Liao, Chih-Feng Cheng, Yu-Min Sun
  • Patent number: 11614479
    Abstract: A device includes FETs with control terminals. A gate driver circuit causes the FETs to turn on and to enter a high-impedance state in response to an OCP signal. A current sense circuit senses an FET current through the FETs and sends the OCP signal to the gate driver circuit when the FET current exceeds an OCP current for longer than an OCP deglitch period. A test sequencer, in response to receiving an external test mode signal, sets the OCP current to a preset OCP test current, sets the OCP deglitch period to a preset OCP deglitch test period, and causes the gate driver circuit to turn on the plurality of FETs.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: March 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Sandeep Kalyadan, Krishnamurthy Ganapathi Shankar, Venkatesh Guduri
  • Patent number: 11614465
    Abstract: A diagnostic test instrument for testing power system equipment may include a chassis having a number of bays capable of receiving test circuitry modules, which may be field inserted by a user desiring to perform a particular test. The instrument may include controller circuitry that may sense in each of the bays whether a respective test circuitry module is inserted therein, and then interrogate respective test circuitry modules in each respective bay to identify a type of the respective test circuitry module. Available testing capabilities may be identified according to the type of each of the respective test circuitry modules identified in respective bays. The controller circuitry may output configuration instructions to test circuitry modules, and respective test ports included in each of the respective test circuitry modules may be selectively illuminated as a configuration instruction to visually identify an assigned functionality of the respective test ports.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: March 28, 2023
    Assignee: DOBLE ENGINEERING COMPANY
    Inventors: Scott Lee Short, Narendra Nagaraj, Fernando D. Gonzalez Tristan, Kevin M. Sullivan, Christopher R. Hamilton
  • Patent number: 11614483
    Abstract: A test apparatus and an automatic test equipment having the same are disclosed. The test apparatus includes a test head having a test area, a socket board combined to the test area of the test, the socket board including a socket body and an active device attached on a first surface of the socket body, the active device configured to operate a semiconductor package, and a heat exchanger arranged on an upper portion of the test head, the heat exchanger being in contact with the socket board.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: March 28, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dahm Yu, Hyunmin Kwon, Jaehyun Kim
  • Patent number: 11609245
    Abstract: Disclosed is a test device for testing a high-frequency and high-speed semiconductor. The test device includes a probe supporting block formed with a tube accommodating portion along a test direction; a conductive shield tube accommodated in the tube accommodating portion; and a probe accommodated and supported in the shield tube without contact, the tube accommodating portion including a conductive contact portion for transmitting a ground signal to the shield tube. When a high-frequency and high-speed semiconductor or the like subject is tested, the test device easily and inexpensively prevents crosstalk between the adjacent signal probes and improves impedance characteristic.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 21, 2023
    Assignee: LEENO INDUSTRIAL INC.
    Inventors: Dong-hoon Park, Jae-hwan Jeong
  • Patent number: 11604212
    Abstract: The disclosed apparatus may include support portions, a frame (such as a base) configured to maintain the support portions in a spaced-apart configuration, a sample holder configured to receive a sample, and a probe assembly including micromanipulators configured to position one or more probes in contact with the sample. The sample holder may rotate between the support portions, and the probe assembly may rotate with the sample holder so that the one or more probes may maintain contact with a sample in the sample holder as the sample holder is rotated, for example, to expose a portion of the sample for processing. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: March 14, 2023
    Assignee: Meta Platforms, Inc.
    Inventors: Pradip Sairam Pichumani, Sandeep Rekhi, Howard Lee Davidson
  • Patent number: 11604219
    Abstract: An example test system includes a test head, and a device interface board (DIB) configured to connect to the test head. The DIB is for holding devices under test (DUTs). The DIB includes electrical conductors for transmitting electrical signals between the DUTs and the test head. Servers are programmed to function as test instruments. The servers are external to, and remote from, the test head and are configured to communicate signals over fiber optic cables with the test head. The signals include serial signals.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: March 14, 2023
    Assignee: TERADYNE, INC.
    Inventors: Roger A. Sinsheimer, Daniel L. Engel, Leal J. Daniels
  • Patent number: 11597502
    Abstract: A blade angle feedback system for an aircraft-bladed rotor rotatable about a longitudinal axis and having an adjustable blade pitch angle is provided. A feedback device is coupled to rotate with the rotor and to move along the axis with adjustment of the blade angle. At least one position marker is affixed to a core of the feedback device and extends along a direction angled relative to the axis. The core is made of a first material having a first magnetic permeability and the position marker comprises a second material having a second magnetic permeability greater than the first magnetic permeability. A sensor is positioned adjacent the feedback device and produces, as the feedback device rotates about the axis, a sensor signal in response to detecting passage of the position marker. A control unit generates a feedback signal indicative of the blade angle in response to the sensor signal.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 7, 2023
    Assignee: PRATT & WHITNEY CANADA CORP.
    Inventor: Dana Tomescu
  • Patent number: 11592479
    Abstract: A test assembly for testing an antenna-in-package (AiP) device includes a socket over a circuit board, where the socket includes an opening for receiving the AiP device; a plunger configured to move along sidewalls of the opening, where during testing of the AiP device, the plunger is configured to cause the AiP device to be pressed towards the circuit board such that the AiP device is operatively coupled to the circuit board via input/output connections of the AiP device and of the circuit board; and a loadboard disposed within the socket and between the plunger and the AiP device, where the loadboard includes a coupling structure configured to be electromagnetically coupled to a transmit antenna and to a receive antenna of the AiP device, so that testing signals transmitted by the transmit antenna are conveyed to the receive antenna externally relative to the AiP device through the coupling structure.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: February 28, 2023
    Assignee: Infineon Technologies AG
    Inventors: Saverio Trotta, Ashutosh Baheti, Reinhard-Wolfgang Jungmaier, Dennis Noppeney
  • Patent number: 11579217
    Abstract: Devices and methods for molecule detection using such devices are disclosed herein. A molecule detection device comprises at least one fluidic channel configured to receive molecules to be detected, a sensor comprising a spin torque oscillator (STO) and encapsulated by a material separating the sensor from the at least one fluidic channel, and detection circuitry coupled to the sensor. At least some of the molecules to be detected are labeled by magnetic nanoparticles (HNPs). A surface of the material provides binding sites for the molecules to be detected. The detection circuitry is configured to detect a frequency or frequency noise of a radio-frequency (RF) signal generated by the STO in response to presence or absence of at least one MNP coupled to one or more binding sites associated with the sensor.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: February 14, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Patrick Braganca, Daniel Bedau
  • Patent number: 11573249
    Abstract: An apparatus for providing a test signal from a device under test (DUT) to a measurement instrument is disclosed. The apparatus includes a probe head configured to receive an electrical signal from the DUT. The probe head includes an electro-optic modulator. The apparatus also includes a control box, which includes an optical source. The optical source is configured to provide an input optical signal to the electro-optic modulator, which is configured to provide an output optical signal based on the electrical signal from the DUT. The control box also includes an optical bias control circuit. Only a bias control signal is provided to the electro-optic modulator.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 7, 2023
    Assignee: Keysight Technologies, Inc.
    Inventors: Ryan Scott, Bogdan Szafraniec, Mike T. Mctigue, Howard Lankford