Patents Examined by Nema Berezny
  • Patent number: 7132734
    Abstract: The present invention provides microelectronic component assemblies and lead frame structures that may be useful in such assemblies. For example, one such lead frame structure may include a set of leads extending in a first direction and a dam bar. Each of the leads may have an outer length and an outer edge. The dam bar may include a plurality of dam bar elements, with each dam bar element being joined to the outer lengths of two adjacent leads. In this example, each dam bar element has an outer edge that extends farther outwardly than the outer edges of the two adjacent leads. The outer edges of the leads and the outer edges of the dam bar elements together define an irregular outer edge of the dam bar. Other lead frame structures and various microelectronic component assemblies are also shown and described.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: November 7, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Mark S. Johnson
  • Patent number: 7041533
    Abstract: One or more stabilizers are disposed on the surface of a semiconductor device component prior to bonding the same to a higher-level substrate. Upon assembly of the semiconductor device component face-down upon a higher-level substrate and joining conductive structures between the contact pads of the semiconductor device component and corresponding contact pads of the higher-level substrate, the stabilizers at least partially stabilize the semiconductor device component on the higher-level substrate to maintain a substantially parallel relation therebetween. The stabilizers can also be positioned and configured to define a minimum, substantially uniform distance between the semiconductor device component and the higher-level substrate. The stabilizers may be preformed structures or fabricated on the surface of the semiconductor device component, such as by way of a stereolithographic method.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: May 9, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Syed Sajid Ahmad
  • Patent number: 7037755
    Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: May 2, 2006
    Assignee: Ziptronix, Inc.
    Inventor: Paul M. Enquist
  • Patent number: 7012321
    Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 14, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Masachika Masuda, Tamaki Wada, Michiaki Sugiyama, Hirotaka Nishizawa, Toshio Sugano, Yasushi Takahashi, Masayasu Kawamura
  • Patent number: 6967392
    Abstract: Described is a method wherein a seal ring is formed by patterning multiple layers each comprised of a dielectric layer with conductive vias covered by a conductive layer. Discontinuities are made in the seal ring encapsulating an integrated circuit. There are no overlaps between different sections of the seal ring thereby reducing coupling of high frequency circuits in the seal ring structures. In addition, the distance between signal pads, circuits and the seal ring are enlarged. Electrical connection is made between deep N-wells and the seal ring. This encapsulates the integrated circuit substrate and reduces signal coupling with the substrate.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: November 22, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Chieh Tsai, Shih Chih Wong
  • Patent number: 6967162
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: November 22, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Yakub Aliyu, Mei Sheng Zhou, John Sudijono, Subhash Gupta, Sudipto Roy, Paul Ho, Yi Xu
  • Patent number: 6964915
    Abstract: A semiconductor component includes a thinned semiconductor die having protective polymer layers on up to six surfaces. The component also includes contact bumps on the die embedded in a circuit side polymer layer, and terminal contacts on the contact bumps in a dense area array. A method for fabricating the component includes the steps of providing a substrate containing multiple dice, forming trenches on the substrate proximate to peripheral edges of the dice, and depositing a polymer material into the trenches. In addition, the method includes the steps of planarizing the back side of the substrate to contact the polymer filled trenches, and cutting through the polymer trenches to singulate the components from the substrate. Prior to the singulating step the components can be tested and burned-in while they remain on the substrate.
    Type: Grant
    Filed: November 21, 2003
    Date of Patent: November 15, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Alan G. Wood, Trung Tri Doan
  • Patent number: 6956287
    Abstract: An electronic component with an electronic circuit and electrical contacts, disposed at least on a first surface of the electronic component, for the electrical bonding of the electronic circuit includes at least one flexible elevation of an insulating material disposed on the first surface, at least one electrical contact disposed on the flexible elevation, and a conduction path disposed on the surface or in the interior of the flexible elevation between the electrical contact and the electronic circuit. A method for producing the electronic component is also provided.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: October 18, 2005
    Assignee: Infineon Technologies AG
    Inventors: Harry Hedler, Alfred Haimerl
  • Patent number: 6949475
    Abstract: Semiconductor devices and methods of fabricating semiconductor devices are disclosed. A disclosed semiconductor device comprises: a semiconductor substrate; an uppermost metal interconnect formed on the semiconductor substrate; an oxide layer formed on the substrate and the uppermost metal interconnect; an aluminum layer formed on the oxide layer; and a stress-relief layer formed on the aluminum layer to thereby prevent cracking of the passivation layer during a subsequent packaging process, to increase reliability of the passivation layer, and to prevent degradation of properties of the semiconductor device.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: September 27, 2005
    Assignee: DongbuAnam Semiconductor, Inc.
    Inventor: Jae Suk Lee
  • Patent number: 6946308
    Abstract: When a crystal layer of III-V Group nitride compound semiconductor is formed, a nitride compound semiconductor layer is first overlaid on a substrate to form a base layer and a III-V Group nitride compound semiconductor represented by the general formula InxGayAlzN (where 0?x?1, 0?y?1, 0?z?1, x+y+z=1) is epitaxially grown on the base layer by hydride vapor phase epitaxy at a deposition pressure of not lower than 800 Torr. By making the deposition pressure not lower than 800 Torr, the crystallinity of the III-V Group nitride compound semiconductor can be markedly improved and its defect density reduced.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: September 20, 2005
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Kazumasa Hiramatsu, Hideto Miyake, Shinya Bohyama, Takayoshi Maeda, Yasushi Iyechika
  • Patent number: 6943102
    Abstract: The method for producing a solder bump transfer sheet of the invention includes the steps of: providing a sheet having a chromium oxide layer containing substantially no iron oxide as the outermost surface; and forming a plurality of solder bumps placed in a predetermined pattern on the chromium oxide layer.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: September 13, 2005
    Assignee: Neomax Co., Ltd.
    Inventor: Masaharu Yamamoto
  • Patent number: 6936489
    Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: August 30, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Tim Murphy, Lee Gotcher
  • Patent number: 6933176
    Abstract: A ball grid array integrated circuit package is manufactured by mounting a semiconductor die, to a surface of a substrate such that bumps on the semiconductor die are electrically connected to conductive traces of the substrate. At least one collapsible spacer is mounted to at least one of a heat spreader, the semiconductor die and the substrate. The heat spreader is fixed to the at least one of the first surface of the substrate and the semiconductor die such that he at least one collapsible spacer is disposed therebetween. A ball grid array is formed on a second surface of the substrate, bumps of the ball grid array being electrically connected to the conductive traces and the integrated circuit package is singulated.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: August 23, 2005
    Assignee: Asat Ltd.
    Inventors: Mohan Kirloskar, Chun Ho Fan, Neil McLellan
  • Patent number: 6933171
    Abstract: The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: August 23, 2005
    Assignee: Intel Corporation
    Inventors: Ming Fang, Valery Dubin, Daoqiang Lu
  • Patent number: 6933611
    Abstract: Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: August 23, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Wayne Kever
  • Patent number: 6930042
    Abstract: A method for producing a semiconductor component includes coating a substrate with a metalization. The metalization is structured in such a way that interconnects are formed at least in an encapsulation region. An encapsulation is applied in the encapsulation region around a previously applied chip. In order to provide sealing during the application of the encapsulation, either the interconnects are structured in such a way that they are interconnected, or a labyrinth structure is formed between the interconnects.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: August 16, 2005
    Assignee: Infineon Technologies AG
    Inventor: Thomas Zeiler
  • Patent number: 6924168
    Abstract: A method and apparatus which provide one or more electromagnetic shield layers for integrated circuit chips containing electromagnetic circuit elements are disclosed. The shield layers may be in contact with the integrated circuit chip, including magnetic memory structures such as MRAMs, or in a flip-chip carrier, or both. A printed circuit board which supports the chip may also have one or more shield layers.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: August 2, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Mark Tuttle
  • Patent number: 6913950
    Abstract: A semiconductor device includes an insulating substrate, a cutout formed in side surfaces of the substrate, a conductive pad formed on the obverse surface of the substrate, an electrode formed on the reverse surface of the substrate, a semiconductor chip mounted on the substrate, and a connector which connects the pad to the electrode. The connector is arranged in the cutout.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: July 5, 2005
    Assignee: Rohm Co., Ltd.
    Inventor: Masahiko Kobayakawa
  • Patent number: 6903375
    Abstract: Through holes are preformed in a ceramic sheet to form recessed portions at corners or side ends of a package 2 used for a solid-state image device. The package is positioned by allowing projections 52, 53, and 54 of a positioning jig 51 to come into contact with end faces 5 and 6 in the recessed portions along their shapes. The accuracy in combining a solid-state image element and a lens block is improved by using a method of positioning a package in which burrs caused when the package is produced by dividing a ceramic baked product do not affect the accuracy.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: June 7, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Eizou Fujii
  • Patent number: 6902956
    Abstract: A semiconductor package structure for a ball grid array type package using a plurality of pieces of adhesive elastomer film to attach a semiconductor die to a substrate having conductive traces in order to alleviate thermal mismatch stress between the semiconductor die and the printed circuit board to which the packaged device is soldered, while maintaining the reliability of the packaged device itself.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: June 7, 2005
    Assignee: Micron Technology, Inc.
    Inventor: Tongbi Jiang