Abstract: A chip and a chip package can transmit information to each other by using a set of converters capable of communicating with each other through the emission and reception of electromagnetic signals. Both the chip and the chip package have at least one such converter physically disposed on them. Each converter is able to (1) convert received electromagnetic signals into electronic signals, which it then may relay to leads on the device on which it is disposed; and (2) receive electronic signals from leads on the device on which it is disposed and convert them into corresponding electromagnetic signals, which it may transmit to a corresponding converter on the other device. Not having a direct physical connection between the chip and the chip package decreases the inductive and capacitive effects commonly experienced with physical bonds.

Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.

Abstract: The invention provides a stubstrate for an electronic device including a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation and which contains a metal oxide having a perovskite structure, a method for manufacturing a substrate for an electronic device, and an electronic device provided with such a substrate for an electronic device. A stubstrate for an electronic device includes a Si substrate, a buffer layer which is formed by epitaxial growth on the Si substrate and which contains a metal oxide having a NaCl structure, and a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation on the buffer layer and which contains a metal oxide having a perovskite structure. The Si substrate is preferably a (100) substrate or a (110) substrate from which a natural oxidation film is not removed.

Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Abstract: A method of manufacturing a semiconductor device, including a first step of placing a resin between one surface of a semiconductor chip, having a plurality of electrodes formed thereon, and a substrate having a wiring pattern formed thereon and defining at least one through-hole in the region in which the semiconductor chip is to be mounted on the substrate, to form a space therebetween that opens into the through-hole, and a second step of pressing either one of the semiconductor chip and the substrate against the other to thereby bond the semiconductor chip to the substrate.

Abstract: The present invention teaches the deposition of a pattern of interconnecting lines and bond pads. Passivation layers are deposited over this metal pattern. A layer of photosensitive polyimide is deposited over the passivation layers. This layer of photosensitive polyimide is patterned, exposed and developed to expose the underlying bonding pads. The remaining polyimide is cured and cross-linked and remains in place to serve as a buffer during further device packaging. Key to the present invention is that the remaining photosensitive polyimide is not removed after the bond pad has been exposed.

Abstract: A method for forming semiconductor device packages that include one or more semiconductor dice, leads in communication with bond pads of each die, and a protective layer, or package, over at least portions of the active surface of each die, and includes electrically exposing the leads through the protective layer so as to facilitate connection thereof to external circuitry. For example, external conductive structures may be secured to the leads through openings in the package. The package may also include protective layers over the back sides or the edges of each semiconductor die. The completed CSP device is precisely encapsulated with minimal lateral dimensions, and has an array of precisely positioned external connectors. A stereolithographic process is used for precisely forming the protective layers of the package. A machine vision system may be used in connection with stereolithographic equipment to locate individual dice, features thereof, or leads.

Abstract: A method for electrically coupling a first set of electrically conductive pads on a first semiconductor substrate to a second set of electrically conductive pads on a second semiconductor substrate is described. Dielectric material of a first thickness is deposited on at least one set of the first and second sets of electrically conductive pads. The first and second semiconductor substrates are then attached together such that such that the first and second sets of pads are substantially aligned parallel to one another and such that the dielectric material is disposed between the first and second sets of electrically conductive pads.

Abstract: The invention is a method of determining a set temperature profile for a method of controlling respective substrate temperatures of a plurality of groups in accordance with respective corresponding set temperature profiles, in a method of heat processing a plurality of substrates that are classified into the plurality of groups.

Abstract: An embodiment of the invention is a metal layer 14 of a back-end module 6 where the height of the interconnects 17 is greater than the height of the dielectric regions 20. Another embodiment of the invention is a method of fabricating a semiconductor wafer 4 where the height of the interconnects 17 is greater than the height of the dielectric regions 20.

Abstract: An image sensor of a quad flat non-leaded package (QFN). The image sensor of a quad flat non-leaded package includes a lead frame having a plurality of leads and a die pad, and the leads are located around a periphery of the die pad. A molding structure is formed around an outer boundary of the leads and located on a first surface of the lead frame. A plurality of bonding pads is formed on the active surface of a chip. A plurality of wires is utilized to electrically connect the bonding pads respectively to bonding portions of the leads on a first surface of the lead frame. A liquid compound is filled in between the chip and the molding structure and covering portions of the leads. A transmittance lid is allocated over the active surface, sealing the space between the molding structure and the lead frame.

Abstract: A light emitting semiconductor package (250) has a semiconductor chip (252) with a surface with one or more light emitting devices (254) formed on or in the surface. A cap (256) is bonded to the surface of the chip (252) to encapsulate the devices (254). The cap has one or more regions (258) transparent to light emitted by the light emitting devices (254). The cap has been bonded to the semiconductor chip (252) at the wafer stage prior to separation of the wafer into individual packages.

Abstract: Supports (40) of microelectronic devices (10) are provided with underfill apertures (60) which facilitate filling underfill gaps (70) with underfill material (74). The underfill aperture may have a longer first dimension (62) and a shorter second dimension (64). In some embodiments, a method of filling the underfill gap (70) employs a removable stencil (80). If so desired, a stencil (80) can be used to fill multiple underfill gaps through multiple underfill apertures in a single pass.

Abstract: A semiconductor component includes a substrate, bonding pads on the substrate, and external contacts bonded to the bonding pads. Exemplary external contacts include solder balls, solder bumps, solder columns, TAB bumps and stud bumps. Preferably the external contacts are arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA). The component also includes a polymer support member configured to strengthen the external contacts, absorb forces applied to the external contacts, and prevent separation of the external contacts from the bonding pads. In a first embodiment, the polymer support member comprises a cured polymer layer on the substrate, which encompasses the base portions of the external contacts. In a second embodiment, the polymer support member comprises support rings which encompass the base portions of the external contacts.

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract: A chip scale package structure formed by adhering a glass sheet having a pattern of holes matching a pattern of bond pads on a semiconductor wafer so that the pattern of holes on the glass sheet are over the pattern of bond pads on the semiconductor wafer. Metallized pads are formed on the glass sheet adjacent to each hole and in one embodiment a conductive trace is formed from each metallized pad on the glass sheet to the bond pad on the semiconductor wafer under the adjacent hole. In a second embodiment, a pad is formed on the glass sheet adjacent to each hole and the pad extends down the sides of the adjacent hole. The hole is filled with a metal plug that electrically connects the pad on the glass sheet to the bond pad on the semiconductor wafer. In each embodiment, a solder ball is formed on each pad on the glass sheet.

Abstract: In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate.

Abstract: A chip scale package design for a flip chip integrated circuit includes a redistribution metal layer upon the upper surface of a semiconductor wafer for simultaneously forming solder bump pads as well as the metal redistribution traces that electrically couple such solder bump pads with the conductive bond pads of the underlying integrated circuit. A patterned passivation layer is applied over the redistribution metal layer. Relatively large, ductile solder balls are placed on the solder bump pads for mounting the chip scale package to a circuit board or other substrate without the need for an underfill material. The back side of the semiconductor wafer can be protected by a coating for mechanical strength during handling. A method of forming such a chip scale package at the wafer processing level is also disclosed.

Abstract: A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound packaging during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.