Abstract: An apparatus and a method for electrically testing a semiconductor wafer, the method including: (i) depositing electrical charges at certain points of a test pattern; (ii) scanning at least a portion of the test pattern such as to enhance charge differences resulting from defects; and (iii) collecting charged particles emitted from the at least scanned portion as a result of the scanning, thus providing an indication about an electrical state of the respective test structure.

Abstract: Provided is, for example, a method for the fabrication of electrical interconnects in semiconductor devices wherein a substrate including two or more transistors having gate regions wherein the gate regions are not exposed (e.g., the gate regions are completely covered by an insulating cap) is provided. An insulating layer overlying the transistors and the active areas is deposited, where upon a hard mask is created and patterned to form a contact plug/interconnect opening over a first active area and a portion of a first transistor immediately adjacent the first active area. A spacer is formed within the contact plug/interconnect opening. Insulating material overlying active areas between transistors is removed. A portion of the gate region of the first transistor is then exposed and interconnect material is deposited within the contact plug/interconnect opening onto the exposed portion of the gate region of the first transistor and the first active area.

Abstract: A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).

Abstract: A semiconductor device is arranged such that a semiconductor chip having electrodes is flip chip mounted on printed substrate pads on a printed wiring substrate by a bump formed on each electrode. The semiconductor chip and the printed wiring substrate are fixed with a thermo-setting resin. A penetration hole is formed within an area where the printed substrate pad contacts each gold bump, and the gold bump has a joint section also on a side face of the penetration hole of the printed substrate pad. With this structure, the semiconductor device has a secure electrical connection between the bump and the metal pattern.

Abstract: A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.

Abstract: A method of manufacturing a light emitting semiconductor package, the method comprising the steps of: obtaining a semiconductor wafer 252 which includes a plurality of light emitting devices 254 residing on or in a surface of the semiconductor wafer 252; forming at least one first hollow cap 256, each first hollow cap 256 formed to provide: a central portion 260 and first perimeter walls extending from the perimeter edge of the central portion with the free edges of the first perimeter walls adapted to be bonded to the surface of the semiconductor wafer 252 to provide a first cavity; at least one region 258 of the central portion 260 which is substantially transparent or translucent to electromagnetic radiation; bonding the at least one first hollow cap 256 to the semiconductor wafer 252, the central portion overlying at least one of the plurality of light emitting devices 254; and, separating the semiconductor wafer 252 with bonded caps 256 into light emitting semiconductor packages 250.

Abstract: A chip package for reduced EMI. In one embodiment, a chip package includes a semiconductor chip mounted on a substrate. First and second horizontal conductors may be present within the substrate. The semiconductor chip is coupled to the first and second horizontal conductors by a first and second pluralities of vertical conductors, respectively. The silicon chip may receive power via the first horizontal conductor and the first plurality of vertical conductors. The first and second horizontal conductors are connected to external connectors by third and fourth pluralities of vertical conductors, respectively. One or more capacitors may be electrically coupled between the first and second horizontal conductors.

Abstract: A semiconductor device manufacturing method is used for packaging a thin semiconductor chip in an economical manner. A semiconductor chip having one electrode terminal, a first member having a first conductor on its surface, and a second member having a second conductor on its surface are prepared. The first and second members are positioned such that the first and second conductors face each other, and the semiconductor chip is held between the members. In this arrangement, one of the first and second conductors is in electrical contact with the first electrode.

Abstract: A device integration method and integrated device. The method may include the steps of directly bonding a semiconductor device having a substrate to an element; and removing a portion of the substrate to expose a remaining portion of the semiconductor device after bonding. The element may include one of a substrate used for thermal spreading, impedance matching or for RF isolation, an antenna, and a matching network comprised of passive elements. A second thermal spreading substrate may be bonded to the remaining portion of the semiconductor device. Interconnections may be made through the first or second substrates. The method may also include bonding a plurality of semiconductor devices to an element, and the element may have recesses in which the semiconductor devices are disposed.

Abstract: A facet-forming layer made of nitride semiconductor containing at least aluminum is formed on a substrate made of gallium nitride (GaN). A facet surface inclined with respect to a C-surface is formed on the surface of the facet-forming layer, and a selective growth layer laterally grows from the inclined facet surface. As a result, the selective growth layer can substantially lattice-match an n-type cladding layer made of n-type AlGaN and grown on the selective growth layer. For example, a laser structure without cracks being generated can be obtained by crystal growth.

Abstract: A plastic land-grid array package, a ball-grid array package, and a plastic leaded package for micromechanical components are fabricated by a molding process characterized by lining the cavity surfaces of the top and bottom mold halves with a protective plastic film, which also protects the surfaces of the components during the molding phase, selectively encapsulating the bonding pads and coupling members of the chip while leaving empty space above the components, and attaching a lid over the components. A molding method as well as a molding apparatus are provided compatible with the sensitivity of the micromechanical devices, yet flexible with regard to the technique used to assemble the chip and the substrate. Furthermore, the method disclosed is flexible with regard to the material and the properties of the substrate.

Abstract: A method for securing a multi-dimensionally constructed chip stack, which has a plurality of part chips which are interconnected at respective contact areas and of which at least one contains functional components, includes the steps of providing respective conductor tracks in the part chips and providing feed-through contacts at the respective contact areas, which in each case interconnect conductor tracks of various part chips so that a continuous electrical signal path running through the part chips is formed. An electrical signal is transmitted from a transmitting device provided at a first end of the electrical signal path to a receiving device provided at a second end of the electrical signal path. When the electrical signal cannot be received, it is determined that the chip stack has been damaged. A device for securing a chip stack and a chip configuration are also provided.

Abstract: A package substrate of, for example, a BGA type or a CSP type, manufactured by carrying out an electrolytic Au plating process without using any plating lead line for formation of bond fingers and solder ball pads, and a method for manufacturing the package substrate.

Abstract: A semiconductor wafer is applied to a support disk via an intervening adhesive layer with the front side of the semiconductor wafer facing the adhesive layer, which is sensitive to a certain exterior factor for reducing its adhesive force; the semiconductor wafer is ground on the rear side; the wafer-and-support combination is applied to a dicing adhesive tape with the so ground rear side facing the dicing adhesive tape, which is surrounded and supported by the circumference by a dicing frame; the certain exterior factor is effected on the intervening adhesive layer to reduce its adhesive force; and the intervening adhesive layer and support disk are removed from the semiconductor wafer or chips without the possibility of damaging the same.

Abstract: Packaged surface mount (SMT) chips having matched top contacts and bottom contacts are stacked. Chip features are selected to provide the desired connectivity between chip layers with a greater ease of manufacture. In one embodiment, additional spacing and routing layers are optionally provided between layers. In another, chips are differentiated by optionally providing different conductor and/or nonvolatile cell configurations. In yet another, a minority of a substrate's contacts are configured for aligning with a dielectric region of a spacing layer or substrate to create very low capacitance signal paths between stacked chips.

Abstract: A micro-scale interconnect device with internal heat spreader and method for fabricating same. The device includes first and second arrays of generally coplanar electrical communication lines. The first array is disposed generally along a first plane, and the second array is disposed generally along a second plane spaced from the first plane. The arrays are electrically isolated from each other. Embedded within the interconnect device is a heat spreader element. The heat spreader element comprises a dielectric material disposed in thermal contact with at least one of the arrays, and a layer of thermally conductive material embedded in the dielectric material. The device is fabricated by forming layers of electrically conductive, dielectric, and thermally conductive materials on a substrate. The layers are arranged to enable heat energy given off by current-carrying communication lines to be transferred away from the communication lines.

Abstract: An inductor obtained by laminating a plurality of ceramic layers having an internal coil conductor, and a thermistor obtained by laminating a plurality of ceramic layers having internal electrodes and having a predetermined resistance-temperature characteristic are laminated via an intermediate insulating layer. Both ends of the internal coil conductor of the inductor and the internal electrodes of the thermistor are connected to a pair of external electrodes. Thus, the inductor and the thermistor are connected in parallel.

Abstract: A vapor-phase growth method for forming a boron-phosphide-based semiconductor layer on a single-crystal silicon (Si) substrate in a vapor-phase growth reactor. The method includes preliminary feeding of a boron (B)-containing gas, a phosphorus (P)-containing gas, and a carrier gas for carrying these gases into a vapor-phase growth reactor to thereby form a film containing boron and phosphorus on the inner wall of the vapor-phase growth reactor; and subsequently vapor-growing a boron-phosphide-based semiconductor layer on a single-crystal silicon substrate. Also disclosed is a boron-phosphide-based semiconductor layer prepared by the vapor-phase growth method.

Abstract: A power semiconductor device includes a portion and an external package enclosing the portion. The portion includes a ceramic board sides provided on the ceramic board defining a space filled with a thermal insulator, and a silicon carbide power semiconductor element enclosed within the thermal insulator. The external package is made of a material having a thermal conductivity lower than that of the side.

Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.