Patents Examined by Ngan Ngo
  • Patent number: 10263078
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Patent number: 10224293
    Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: March 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
  • Patent number: 10205075
    Abstract: A light emitting device and method of forming the same, the light emitting device including: a substrate, a buffer layer disposed on the substrate, a semiconductor mesa disposed on the buffer layer and including a first semiconductor layer, a light emitting active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the first semiconductor layer, a contact layer disposed on an upper surface of the mesa, a passivation layer covering sidewalls of the mesa and the contact layer, and a cap structure including a reflective layer covering an upper surface of the contact layer, and a solder layer including a recess in which the reflective layer is disposed.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 12, 2019
    Assignee: GLO AB
    Inventors: Anusha Pokhriyal, Mariana Munteanu, Fariba Danesh
  • Patent number: 10204842
    Abstract: A semiconductor package includes a lead frame having a die attach pad and a plurality of leads. A die is attached to the die attach pad and the electrically connected to the plurality of leads. The die includes a plurality of bond pads along a periphery of the die and a bond pad strip surrounding a circuit in the die. A first plurality of bond wires is bonded between first opposite sides of the bond pad strip. The first plurality of bond wires is aligned in a first direction. A second plurality of bond wires is bonded between second opposite sides of the bond pad strip. The second plurality of bond wires is aligned in a second direction. Mold compound covers portions of the lead frame, the die, the bond pad strip, the first plurality of bond wires and the second plurality of bond wires.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: February 12, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Siva Prakash Gurrum, Amit Sureshkumar Nangia
  • Patent number: 10199494
    Abstract: The present disclosure provides a laterally diffused metal-oxide-semiconductor (LDMOS) device. The LDMOS device includes a plurality of fin structures formed on a substrate including a first device region, a second device region, and an isolation region sandwiched between the two regions. An opening is formed in the fin structures in the isolation region. The LDMOS device further includes an isolation layer formed in the opening and covering the sidewall of the opening formed by a portion of each fin structure in the first device region. The isolation layer exposes top surfaces of the plurality of fin structures. Moreover, the LDMOS device also includes a gate structure formed across each fin structure in the first device region. The gate structure covers a portion of the sidewall and the top surfaces of the fin structure formed in the first device region and also covers the top surface of the isolation layer.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 5, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fei Zhou
  • Patent number: 10192790
    Abstract: A method for fabricating an SRAM device includes providing a base substrate including a pull up transistor (PUT) region and a pull down transistor (PDT) region, forming a gate dielectric layer, forming a first work function (WF) layer using a P-type WF material, removing the first WF layer formed in the PDT region, forming a second WF layer using a P-type WF material on the first WF layer in the PUT region and on the gate dielectric layer in the PDT region, removing the second WF layer formed in the PDT region, forming a third WF layer using an N-type WF material on the top and the sidewall surfaces of the second WF layer in the PUT region, the sidewall surface of the first WF layer in the PUT region, and the gate dielectric layer in the PDT region, and forming a gate electrode layer on the third WF layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: January 29, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • Patent number: 10192937
    Abstract: A display device includes a substrate including a display area and a non-display area, a pixel unit provided in the display area, and including a first pixel column including a plurality of pixels and a second pixel column including a plurality of pixels displaying a different color from a color of the first pixel column, and data lines which are respectively connected to the first pixel column and the second pixel column, and respectively apply data signals to the first pixel column and the second pixel column, wherein the data line connected to the first pixel column includes sub lines and the data line connected to the second pixel column includes sub lines.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Deuk Jong Kim, Ji Hye Heo, Za Il Lhee, Mi Na Jung
  • Patent number: 10170577
    Abstract: Vertical transport field effect transistors (FETs) having improved device performance are provided. Notably, vertical transport FETs having a gradient threshold voltage are provided. The gradient threshold voltage is provided by introducing a threshold voltage modifying dopant into a physically exposed portion of a metal gate layer composed of an n-type workfunction TiN. The threshold voltage modifying dopant changes the threshold voltage of the original metal gate layer.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Takashi Ando, Jingyun Zhang, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10170618
    Abstract: A method of forming a vertical transport fin field effect transistor, including, forming a bottom source/drain layer at the surface of the substrate, forming one or more channels on the bottom source/drain layer, where the channels extend away from the bottom source/drain layer, forming a gate structure on each of the one or more channels, and forming a top source/drain segment on the top surface of each of the one or more channels, wherein either each of the top source/drain segments or the bottom source/drain layer has a larger bandgap than the other of the bottom source/drain layer or each of the top source/drain segments.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Peng Xu, Chen Zhang
  • Patent number: 10170327
    Abstract: Methods and structures for fabricating fins for multigate devices are disclosed. In accordance with one method, a plurality of sidewalls are formed in or on a plurality of mandrels over a semiconductor substrate such that each of the mandrels includes a first sidewall composed of a first material and a second sidewall composed of a second material that is different from the first material. The first sidewall of a first mandrel of the plurality of mandrels is selectively removed. In addition, a pattern composed of remaining sidewalls of the plurality of sidewalls is transferred onto an underlying layer to form a hard mask in the underlying layer. Further, the fins are formed by employing the hard mask and etching semiconducting material in the substrate.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin
  • Patent number: 10163818
    Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Jing-Cheng Lin, Tsei-Chung Fu
  • Patent number: 10163817
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Yen-Yao Chi
  • Patent number: 10164151
    Abstract: A method for producing a nitride semiconductor device. The method comprises providing a substrate made of a material other than a nitride semiconductor. The material has a hexagonal crystal structure. An upper face of the substrate has at least one flat section. The method further comprises growing a first nitride semiconductor layer on the upper face of the substrate. The first nitride semiconductor layer is made of monocrystalline AlN. The first nitride semiconductor layer has an upper face that is a +c plane. The first nitride semiconductor layer has a thickness in a range of 10 nm to 100 nm. The method further comprises growing a second nitride semiconductor layer on the upper face of the first nitride semiconductor layer. The second nitride semiconductor layer is made of InXAlYGa1-X-YN (0?X, 0?Y, X+Y<1).
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: December 25, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Atsuo Michiue
  • Patent number: 10147677
    Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: December 4, 2018
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Patent number: 10134645
    Abstract: A stress monitoring device includes an anchor structure, a freestanding structure and a Vernier structure. The anchor structure is over a substrate. The freestanding structure is over the substrate, wherein the freestanding structure is connected to the anchor structure and includes a free end suspended from the substrate. The Vernier structure is over the substrate and adjacent to the free end of the freestanding structure, wherein the Vernier structure comprises scales configured to measure a displacement of the free end of the freestanding structure.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: November 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chen-Fa Lu, Cheng-Yuan Tsai
  • Patent number: 10121762
    Abstract: Wafer bonding methods and wafer bonding structures are provided. An exemplary wafer bonding method includes providing a first wafer; forming a first interlayer dielectric layer and a first bonding layer passing through the first interlayer dielectric layer on the surface of the first wafer; providing a second wafer; forming a second interlayer dielectric layer and a second bonding layer passing through the second interlayer dielectric layer on surface of the second wafer; forming a self-assembling layer on at least one of a surface of the first interlayer dielectric layer and a surface of the second interlayer dielectric layer; and bonding the first wafer with the second wafer, the first bonding layer and the second bonding layer being fixed with each other, and the first interlayer dielectric layer and the second interlayer dielectric layer being fixed with each other by the self-assembling molecular layer.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: November 6, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Fu Cheng Chen
  • Patent number: 10115800
    Abstract: A method of manufacturing a bipolar junction transistor (BJT) structure is provided. Pattern etching through a second semiconductor layer and recessing a silicon germanium layer are performed to form a plurality of vertical fins each including a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on a first semiconductor layer above a substrate. First spacers are formed on sidewalls of the plurality of vertical fins. Exposed silicon germanium layer above the first semiconductor layer is directionally etched away. A germanium oxide layer is conformally coated to cover all exposed top and sidewall surfaces. Condensation annealing followed by silicon oxide strip is performed. The first spacers, remaining germanium oxide layer and the hard mask pattern are removed. A dielectric material is deposited to isolate the plurality of vertical fins.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: October 30, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seyoung Kim, Choonghyun Lee, Injo Ok, Soon-Cheon Seo
  • Patent number: 10108054
    Abstract: A liquid crystal display device includes a base unit, a gate line disposed on the base unit, a data line disposed on the base unit and crossing the gate line while being insulated from the gate line, a shielding electrode disposed on the data line and overlapping the data line and isolated from the pixel electrode and a conductive bar, the conductive bar disposed on the same layer as that on which the shielding electrode is disposed, isolated from the shielding electrode, and extending in parallel to the data line.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: October 23, 2018
    Assignee: SAMSUNG DISPLAY CO. LTD.
    Inventors: Hak Sun Chang, Cheol Shin, Ki Chul Shin, Se Hyun Lee, Yun Seok Lee
  • Patent number: 10109793
    Abstract: The present disclosure relates to a memory cell having a multi-layer bottom electrode with an insulating core that provides for good gap fill ability, and an associated method of formation. In some embodiments, the memory cell includes a bottom electrode having an insulating material surrounded by a conductive material. A dielectric data storage layer is arranged over the bottom electrode, and a top electrode is arranged over the dielectric data storage layer.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jen-Sheng Yang, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10109522
    Abstract: One or more techniques or systems for forming a semiconductor structure having a gap are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: October 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Nien Su, Hsiang-Wei Lin