Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.

Abstract: A semiconductor device manufacturing method includes: vertically arranging and storing a plurality of substrates in a processing container and forming a condition where at least an upper region or a lower region relative to a substrate disposing region where the plurality of substrates are arranged is blocked off by an adaptor; and while maintaining the condition, forming films on the plurality of substrates by performing a cycle including the following steps a predetermined number of times in a non-simultaneous manner: supplying source gas to the plurality of substrates in the processing container from the side of the substrate disposing region; discharging the source gas from the interior of the processing container via exhaust piping; supplying reaction gas to the plurality of substrates in the processing container from the side of the substrate disposing region; and discharging the reaction gas from the interior of the processing container via the exhaust piping.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface disposed to oppose the active surface; a dummy chip disposed in the through-hole and spaced apart from the semiconductor chip; a second connection member disposed on the first connection member, the dummy chip, and the active surface of the semiconductor chip; and an encapsulant encapsulating at least portions of the first connection member, the dummy chip, and the inactive surface of the semiconductor chip. The first connection member and the second connection member include, respectively, redistribution layers electrically connected to the connection pads.

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

Abstract: Embodiments disclosed herein relate to an electroluminescence display device including a first electrode, a second electrode facing the first electrode, an emission layer between the first electrode and the second electrode, and a bank layer defining the emission layer. The bank layer may be disposed between the first electrode and the second electrode. The bank layer may include a first bank layer and a second bank layer. The second bank layer may include a black pigment. The first bank layer may be closer to the first electrode than the second bank layer, and the first bank layer may have a lower permittivity than the second bank layer.

Abstract: The patterning technique used for forming sophisticated metallization systems of semiconductor devices may be monitored and evaluated more efficiently by incorporating at least one via line feature into the die seal. In this manner, high statistical significance may be obtained compared to conventional strategies, in which the respective test structures for evaluating patterning processes may be provided at specific sites in the frame region and/or die region. Moreover, by providing a “long” via line feature, superior sensitivity for variations of depth of focus may be achieved.

Abstract: An object is to provide an imaging device with high efficiency of transferring charge corresponding to imaging data. The imaging device includes first to fifth conductors, first and second insulators, an oxide semiconductor, a photoelectric conversion element, and a transistor. The first conductor is in contact with a bottom surface and a side surface of the first insulator. The first insulator is in contact with a bottom surface of the oxide semiconductor. The oxide semiconductor is in contact with bottom surfaces of the second and third conductors and the second insulator. Each of the second and third conductors is in contact with the bottom surface and a side surface of the second insulator. The second insulator is in contact with bottom surfaces of the fourth and fifth conductors. The first conductor has regions overlapped by the fourth and fifth conductors. The second conductor has a region overlapped by the fourth conductor. The third conductor has a region overlapped by the fifth conductor.

Abstract: There is provided a solid-state image pickup device that includes a functional region provided with an organic film, and a guard ring surrounding the functional region.

Abstract: This disclosure relates to an OLED display apparatus and the preparation method thereof. The OLED display apparatus comprises, from the bottom to the top, a substrate, an OLED device, a thin film inner layer, an ethylcellulose layer, and a thin film outer layer. By adding a hydrophobic ethylcellulose layer with a photosensitive material and a singlet oxygen receptor dissolved therein on the basis of current thin film packaging, this invention can have the functions of water vapor barrier and oxygen absorption so as to improve the service life of devices.

Abstract: The solar cell includes: a first metal seed layer and a first plating layer provided on a first surface of a photoelectric conversion section; a second metal seed layer provided on a second surface of the photoelectric conversion section; and a third metal seed layer and a third plating layer provided on the lateral surface and the peripheral edge of the second surface of the photoelectric conversion section. The first metal seed layer is in electrical continuity with the third metal seed layer, while the second metal seed layer is in electrical non-continuity with the third metal seed layer. By supplying electricity to at least one of the first metal seed layer and the third metal seed layer, the first plating layer and the third plating layer are formed simultaneously.

Abstract: A substrate processing device capable of stabilizing an etching amount of a metal film provided on a substrate is provided. The substrate processing device includes a first container, a second container and a control unit. The first container stores a first liquid in which an acid solution containing phosphoric acid and water are mixed. The first liquid is capable of etching a metal film provided on a substrate. The second container stores a second liquid containing water. The control unit controls supply of the second liquid from the second container to the first container such that a water concentration of the first liquid increases over time corresponding to change in a concentration of the phosphoric acid in the first liquid.

Abstract: A semiconductor memory device according to an embodiment comprises: when three directions intersecting each other are assumed to be first through third directions, and two directions intersecting each other in a plane extending in the first and second directions are assumed to be fourth and fifth directions, a memory cell array including: a conductive layer stacked in the third direction above a semiconductor substrate and having a first region; and a first columnar body penetrating the first region of the conductive layer in the third direction and including a semiconductor film, the first columnar body having a cross-section along the first and second directions in which, at a first position which is a certain position in the third direction, a length in the fourth direction is shorter than a length in the fifth direction.

Abstract: An electronic device includes a thyristor having an anode, a cathode, a first bipolar transistor disposed on the anode side. A second bipolar transistor is disposed on the cathode side. These two bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is coupled between the collector region and the emitter region of the second bipolar transistor. The transistor has a gate region connected to the cathode via a resistive semiconductor region incorporating at least a part of the base region of the second bipolar transistor.

Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

Abstract: A display apparatus includes a flexible substrate, a light-emitting diode (LED), and a partitioning wall pattern. The flexible substrate includes a concavo-convex portion. The flexible substrate has a first elasticity. The LED is disposed on the concavo-convex portion. The partitioning wall pattern substantially surrounds the LED at a predetermined distance from the LED in a plan view. The partitioning wall pattern has a second elasticity less than the first elasticity.

Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract: A method for is used for forming a semiconductor device. The method includes forming an ILD layer on a substrate and a buffer layer on the ILD layer, wherein at least one contact is formed in the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.

Abstract: The semiconductor structure includes a semiconductor substrate; field-effect devices disposed on the semiconductor substrate, wherein the field-effect devices include gates with elongated shape oriented in a first direction; a first metal layer disposed over the gates; a second metal layer disposed over the first metal layer; and a third metal layer disposed over the second metal layer. The first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction. The second metal layer includes a plurality of second metal lines oriented in the first direction. The third metal layer includes a plurality of third metal lines oriented in the second direction. The first metal lines have a first thickness, the second metal lines have a second thickness, the third metal lines have a third thickness, and the second thickness is less than the first thickness and the third thickness.

Abstract: A semiconductor device includes an active region disposed in a semiconductor substrate and an uppermost metal level including metal lines, where the uppermost metal level is disposed over the semiconductor substrate. Contact pads are disposed at a major surface of the semiconductor device, where the contact pads are coupled to the metal lines in the uppermost metal level. An isolation region separates the contact pads disposed at the major surface. Adjacent contact pads are electrically isolated from one another by a portion of the isolation region. Reflective structures are disposed between the upper metal level and the contact pads, where each of the reflective structures that is directly over the active region completely overlaps an associated portion of the isolation region separating the contact pad.

Abstract: Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.