Abstract: A manufacturing method of a patterned structure of a semiconductor device includes following steps. A plurality of support features are formed on a substrate. A first conformal spacer layer is formed on the support features and a surface of the substrate, a second conformal spacer layer is formed on the first conformal spacer layer, and a covering layer is formed on the second conformal spacer layer. A gap between the support features is filled with the first conformal spacer layer, the second conformal spacer layer, and the covering layer. A first process is performed to remove a part of the covering layer, the second conformal spacer layer, and the first conformal spacer layer. A second process is performed to remove the support features or the first conformal spacer layer between the support feature and the second conformal spacer layer to expose a part of the surface of the substrate.

Abstract: In one implementation, a reliable and robust electrical contact includes a contact pad patterned from a first metal layer situated over a surface of an active die, and multiple dielectric islands situated over the contact pad. The dielectric islands are spaced apart from one another by respective segments of a second metal layer formed between and over the dielectric islands. The contact pad, the dielectric islands, and the second metal layer provide the reliable and robust electrical contact.

Abstract: Semiconductor packages and methods of manufacturing semiconductor packages are described herein. In certain embodiments, the semiconductor package includes a housing including a first compartment and a second compartment, the first and second compartments being divided from one another. The semiconductor package can also include an integrated device die disposed in the first compartment, and a radio frequency (RF) absorber disposed in the second compartment.

Abstract: A semiconductor structure is provided in which the diffusion of arsenic is retarded. The structure includes a strain relaxed silicon germanium alloy buffer layer located on a surface of a silicon substrate. A boron-containing p-well region is located in a first region of a carbon doped silicon germanium alloy layer and on a first portion of the strain relaxed silicon germanium alloy buffer layer, and a phosphorus-containing n-well region is located in a second region of the carbon doped silicon germanium alloy layer and on a second portion of the strain relaxed silicon germanium alloy buffer layer. A tensily strained silicon material is located on a surface of the p-well region, and a compressively strained germanium-containing material is located on a surface of the n-well region.

Abstract: Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons.

Abstract: A light emitting device is provided that may include a substrate, a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer provided on the substrate, a first electrode on the first conductive semiconductor layer, and a schottky guide ring configured to surround the first electrode and directly connect with the first conductive semiconductor layer.

Abstract: Methods and apparatus for thinner package on package (“PoP”) structures. A structure includes a first integrated circuit package including at least one integrated circuit device mounted on a first substrate and a plurality of package on package connectors extending from a bottom surface; and a second integrated circuit package including at least another integrated circuit device mounted on a second substrate and a plurality of lands on an upper surface coupled to the plurality of package on package connectors, and a plurality of external connectors extending from a bottom surface; wherein at least the second substrate is formed of a plurality of layers of laminated dielectric and conductors. In another embodiment a cavity is formed on the bottom surface of the first substrate and a portion of the another integrated circuit extends partially into the cavity. Methods for making the PoP structures are disclosed.

Abstract: According to one embodiment, the plurality of contact vias extend in the stacking direction in the insulating layer, and are in contact with the end parts of the electrode layers. The plurality of second columnar parts extend in the stacking direction in the second stacked part, and include a plurality of second semiconductor bodies being different in length in the stacking direction.

Abstract: According to one embodiment, a magnetoresistive memory device includes a stacked layer structure includes a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, and a third magnetic layer provided on the first magnetic layer, which is opposite the nonmagnetic layer. The third magnetic layer includes a first magnetic material portion and a second magnetic material portion provided between the stacked layer structure and the first magnetic material portion. The saturation magnetization of the second magnetic material portion is smaller than that of the first magnetic material portion.

Abstract: An array substrate, a fault line repair method thereof, and a display device are provided. The array substrate includes: a base substrate; a gate line and a signal line which are arranged on the base substrate, adjacent gate lines and adjacent signal lines crossing with each other to define a pixel region; and a pixel electrode located in the pixel region. The array substrate further includes a common electrode corresponding to the pixel electrode. The common electrode includes: a frame; a first strip-shaped connection part arranged in the frame and having both ends thereof connected with the frame; and a second strip-shaped connection part connected with the first strip-shaped connection part in a crossed manner and having both ends thereof disconnected from the frame. The signal line is parallel with the second strip-shaped connection part and located directly above or directly under the second strip-shaped connection part.

Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask formed from a third insulating film; a third step of forming a second hard mask on a side wall of the first hard mask, and forming a second dummy gate; a fourth step of forming a sidewall and forming a second diffusion layer; a fifth step of depositing an interlayer insulating film, exposing upper portions of the second dummy gate and the first dummy gate, removing the second dummy gate and the first dummy gate, forming a first gate insulating film, and forming a gate electrode and a gate line; and a sixth step of forming a first contact and a second contact.

Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.

Abstract: A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.

Abstract: According to one embodiment, an insulator includes a material including barium and hafnium oxide. The material has a crystal structure of a space group Pbc21.

Abstract: In one embodiment, an integrated circuit includes an array of active structures, an array of dummy structures and multiple well-tap structures. The array of dummy structures surrounds the array of active structures. The well-tap structures may be interposed between the array of active structures and the array of dummy structures. In one embodiment, each of the well-tap structures may include a well, a diffusion region and a gate-like structure. The well may be formed in a substrate and is of a first doping type. The diffusion region may be formed in the well and is also of the first doping type. The gate-like structure may be formed above the substrate and adjacent to the diffusion region.

Abstract: A mounting substrate includes: a base; and at least one pair of wiring patterns disposed apart from each other on the base. At least one of the wiring patterns has a mounting portion, which is configured to support an electronic part thereon and which is rectangular in a plan view. The at least one of the wiring patterns defines a hole, which exposes a part of the base and which is disposed in at least a part of an outer edge of the mounting portion.

Abstract: A fuse package may include a first lead frame, a second lead frame spaced apart from the first lead frame, a package body configured to cover at least a portion of the first lead frame and at least a portion of the second lead frame, a wire fuse mounted on the first lead frame and the second lead frame, and configured to electrically connect the two lead frames, and an encapsulator configured to cover the wire fuse.

Abstract: A semiconductor device according an embodiment includes a GaN layer, a GaN-based semiconductor layer provided on the GaN layer and having a wider band gap than the GaN layer, a source electrode electrically connected to the GaN-based semiconductor layer, a drain electrode electrically connected to the GaN-based semiconductor layer, a gate electrode provided in the GaN-based semiconductor layer between the source electrode and the drain electrode, and a gate insulating film provided at least between the GaN layer and the gate electrode, the gate insulating film including a first insulating film and a second insulating film, the first insulating film provided on the GaN layer, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the first insulating film including nitrogen, the second insulating film provided between the first insulating film and the gate electrode, the second insulating film including oxygen.

Abstract: A method of manufacturing an electronic device may include: forming at least one electronic component in a substrate; forming a contact pad in electrical contact with the at least one electronic component; wherein forming the contact pad includes: forming a first layer over the substrate; planarizing the first layer to form a planarized surface of the first layer; and forming a second layer over the planarized surface, wherein the second layer has a lower porosity than the first layer.

Abstract: Methods and apparatus to provide a magnetic field sensor device including a magnetic sensor element, a die having wafer bumps, wherein the magnetic sensor element is positioned in relation to the die, and conductive leadfingers having respective portions electrically connected to the wafer bumps. In embodiments, the device includes a region about the magnetic sensor element that does not contain electrically conductive material for preventing eddy current flow.