Patents Examined by Ngan Ngo
  • Semiconductor light-emitting device
    Patent number: 9793436
    Abstract: A semiconductor light-emitting device comprises an epitaxial structure for emitting a light and comprises an edge, a first portion and a second portion surrounding the first portion, wherein a concentration of a doping material in the second portion is higher than that of the doping material in the first portion, a main light-extraction surface on the epitaxial structure and comprises a first light-extraction region corresponding to the first portion and a second light-extraction region corresponding to the second portion and an edge, wherein the second portion is between the edge and the first portion.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: October 17, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Hsin-Chih Chiu, Shih-I Chen, You-Hsien Chang, Hao-Min Ku, Ching-Yuan Tsai, Kuan-Chih Kuo, Chih-Hung Hsiao, Rong-Ren Lee
  • Method for structuring a substrate using a protection layer as a mask
    Patent number: 9793119
    Abstract: According to various embodiments, a method of processing a substrate may include: disposing a viscous material over a substrate including at least one topography feature extending into the substrate to form a protection layer over the substrate; adjusting a viscosity of the viscous material during a contacting period of the viscous material and the substrate to stabilize a spatial distribution of the viscous material as disposed; processing the substrate using the protection layer as mask; and removing the protection layer after processing the substrate.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: October 17, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Mischitz, Markus Heinrici, Florian Bernsteiner
  • Fin pitch scaling for high voltage devices and low voltage devices on the same wafer
    Patent number: 9786563
    Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 10, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Method of cleaning post-etch residues on a copper line
    Patent number: 9786489
    Abstract: A method of cleaning post-etch residues on a copper line includes providing a copper line which is divided into a first region and a second region. A dielectric layer is formed on the copper line. After that, the dielectric layer is etched to form openings in the dielectric layer. A number of openings within the first region is more than a number of openings in the second region. During the etching process, a potential difference is formed between the first region and the second region of the copper line. Finally, the dielectric layer and the copper line are cleaned by a solution with a PH value. The PH value has a special relation with the potential difference.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: October 10, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming Sheng Xu, Ching-Long Tsai, Hua-Kuo Lee, Guangjun Huang
  • Semiconductor light emitting device
    Patent number: 9786819
    Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 10, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Masakazu Takao, Mitsuhiko Sakai, Kazuhiko Senda
  • Fin pitch scaling for high voltage devices and low voltage devices on the same wafer
    Patent number: 9780091
    Abstract: A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second plurality of fin structures having a second width in a second region of the substrate, the second width being less than the first width. A first gate structure is formed on the first plurality of fin structures including a first high-k gate dielectric that is in direct contact with a channel region of the first plurality of fin structures and a first gate conductor. A second gate structure is formed on the second plurality of fin structures including a high voltage gate dielectric that is in direct contact with a channel region of the second plurality of fin structures, a second high-k gate dielectric and a second gate conductor.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: October 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Packaged IC with solderable sidewalls
    Patent number: 9780060
    Abstract: A packaged IC wherein a portion of the sidewalls of the packaged IC are solderable metal. A method of forming a packaged IC wherein a portion of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal. A method of forming a packaged IC wherein all of the sidewalls of the wire bond pads or the flip chip pads that are exposed by sawing during singulation are solderable metal and a portion of sidewall of the molding compound is solderable metal.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: October 3, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yong Lin, Vikas Gupta, Rongwei Zhang
  • Method of fabricating chip package with laser
    Patent number: 9780050
    Abstract: A chip package included a chip, a first though hole, a laser stop structure, a first isolation layer, a second though hole and a conductive layer. The first though hole is extended from the second surface to the first surface of the chip to expose a conductive pad, and the laser stop structure is disposed on the conductive pad exposed by the first through hole, which an upper surface of the laser stop structure is above the second surface. The first isolation layer covers the second surface and the laser stop structure, and the first isolation layer has a third surface opposite to the second surface. The second though hole is extended from the third surface to the second surface to expose the laser stop structure, and a conductive layer is on the third surface and extended into the second though hole to contact the laser stop structure.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: October 3, 2017
    Assignee: XINTEC INC.
    Inventors: Ying-Nan Wen, Chien-Hung Liu, Shih-Yi Lee, Ho-Yin Yiu
  • Semiconductor device, layout system, and standard cell library
    Patent number: 9780082
    Abstract: A semiconductor device includes a substrate, a first transistor gated by an inverted voltage level of a first input signal to pull up a first node, a second transistor gated by a voltage level of a second input signal to pull down the first node, a third transistor gated by an inverted voltage level of the second input signal to pull up the first node, a fourth transistor gated by a voltage level of the first input signal to pull down the first node, a fifth transistor gated by the voltage level of the second input signal to pull down a second node, a sixth transistor gated by the inverted voltage level of the first input signal to pull up the second node, a seventh transistor gated by the voltage level of the first input signal to pull down the second node, and an eighth transistor gated by the inverted voltage level of the second input signal to pull up the second node.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: October 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Seong Lee, Dae-Young Moon, Min-Su Kim
  • Method of manufacturing a semiconductor device to prevent occurrence of short-channel characteristics and parasitic capacitance
    Patent number: 9773872
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: September 26, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Method for structuring a substrate
    Patent number: 9768023
    Abstract: According to various embodiments, a method of processing a substrate may include: disposing a viscous material over a substrate including at least one topography feature extending into the substrate to form a protection layer over the substrate; adjusting a viscosity of the viscous material during a contacting period of the viscous material and the substrate to stabilize a spatial distribution of the viscous material as disposed; processing the substrate using the protection layer as mask; and removing the protection layer after processing the substrate.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: September 19, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Mischitz, Markus Heinrici, Florian Bernsteiner
  • Integrated circuits with thermal isolation and temperature regulation
    Patent number: 9761543
    Abstract: Integrated circuits with a molded package including a cavity and a semiconductor die spaced from an interior surface of the molded package within the cavity. The semiconductor die includes one or more electrical components, a thermal control component to control the temperature of the electrical component, and a driver to provide a current or voltage signal to the thermal control component at least partially according to a setpoint signal.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: September 12, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Barry Jon Male, Benjamin Cook, Robert Alan Neidorff, Steve Kummerl
  • Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device
    Patent number: 9761509
    Abstract: A method for is used for forming a semiconductor device having a through-substrate via. The method includes providing a preliminary structure having an ILD layer on a substrate and a buffer layer on the ILD layer; forming an opening through the buffer layer, the ILD layer, and the substrate; forming a liner structure layer over the substrate, wherein an exposed surface of the opening is covered by the liner structure layer; depositing a conductive material over the substrate to fill the opening; performing a polishing process, to polish over the substrate and stop at the buffer layer, wherein the liner structure layer and the conductive material remaining in the opening form a conductive via; performing an etching back process, to remove the buffer layer and expose the ILD layer, wherein a top portion of the conductive via is also exposed and higher than the ILD layer.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: September 12, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Kuei-Sheng Wu, Ming-Tse Lin
  • Semiconductor device having fin-shaped semiconductor layer
    Patent number: 9755053
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask formed from a third insulating film; a third step of forming a second hard mask on a side wall of the first hard mask, and forming a second dummy gate; a fourth step of forming a sidewall and forming a second diffusion layer; a fifth step of depositing an interlayer insulating film, exposing upper portions of the second dummy gate and the first dummy gate, removing the second dummy gate and the first dummy gate, forming a first gate insulating film, and forming a gate electrode and a gate line; and a sixth step of forming a first contact and a second contact.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 5, 2017
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Integrated circuit package
    Patent number: 9754913
    Abstract: Integrated circuit package including an integrated circuit, external connection elements (3) connected to the integrated circuit, a package material (2) enclosing the integrated circuit, and a mechanical element (5, 6, 7) allowing a mechanical connection of a further element to the integrated circuit package (1). The mechanical element (5, 6, 7) is e.g. an attachment element (5); a mechanical element (5), optionally with a thread; a bushing element; a bearing element (7); an electrical connector (6).
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: September 5, 2017
    Assignee: SENCIO B.V.
    Inventor: Jurgen Leonardus Theodorus Maria Raben
  • Structure of integrated inductor
    Patent number: 9748326
    Abstract: This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: August 29, 2017
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Hsiao-Tsung Yen, Yuh-Sheng Jean, Ta-Hsun Yeh
  • Through-body via liner deposition
    Patent number: 9748180
    Abstract: Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the opposite side of the substrate (e.g., bottom), or from one internal layer of the substrate to another internal layer. A liner is disposed between the substrate and each TSV. The liner is formed of multiple alternating layers of dissimilar insulation films (e.g., tensile films and compressive films) sandwiched together.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: August 29, 2017
    Assignee: INTEL CORPORATION
    Inventors: Puneesh Puri, Jiho Kang, James Y. Jeong
  • Vertical memory structure with array interconnects and method for producing the same
    Patent number: 9741769
    Abstract: Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: August 22, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Luiz M. Franca-Neto, Jeffrey Lille
  • Encapsulated semiconductor package and method of manufacturing thereof
    Patent number: 9741617
    Abstract: Encapsulated semiconductor packages and methods of production thereof. As a non-limiting example, a semiconductor package may be produced by partially dicing a wafer, molding the partially diced wafer, and completely dicing the molded and partially diced wafer.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: August 22, 2017
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Bora Baloglu, Curtis Zwenger, Ron Huemoeller
  • Integrated interposer solutions for 2D and 3D IC packaging
    Patent number: 9741649
    Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: August 22, 2017
    Assignee: INVENSAS CORPORATION
    Inventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram, Guilian Gao