Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

Abstract: An embodiment discloses an electronic device, including: a processing component; and a heat dissipation unit thermally coupled to the processing component, the heat dissipation unit comprising: a first thermal conductive layer that directs heat that is generated by the processing component away from the processing component in a first direction, and a second layer disposed in relation to the first thermal conductive layer, where the second layer has a lower thermal conductivity as compared with the first thermal conductive layer in the first direction. Other aspects are described and claimed.

Abstract: A heat sink includes a heat sink base, a first fin, and a second fin. The spacing between the base and the first fin and the second fin, restively, may be adjusted by rotating a threaded rod. The threaded rod includes a first threaded knurl that is engaged with the first fin and a second threaded knurl that is engaged with the second fin. The thread pitch of the first threaded knurl and the second threaded knurl may differ. For example, the pitch of the first threaded knurl may be smaller than the pitch of the second threaded knurl if the first fin is located nearest the heat sink base relative to the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.

Abstract: There is provided a solid-state image pickup device that includes a functional region provided with an organic film, and a guard ring surrounding the functional region

Abstract: A light emitting diode includes an insulating substrate, a first MgO layer, a semiconductor carbon nanotube layer, a second MgO layer, a functional dielectric layer, a first electrode, and a second electrode. The semiconductor carbon nanotube layer has a first surface and a second surface. The first MgO layer coats entire the first surface. The second surface is divided into a first region and a second region. The first region is coated with the second MgO layer. The second MgO layer is covered by the functional dielectric layer. The second region is exposed. The first electrode is electrically connected to the first region. The second electrode is electrically connected to the second region.

Abstract: The method of manufacturing a semiconductor device includes receiving a substrate. The substrate comprises at least one chip region and at least one scribe line next to the chip region, and each chip region comprises an active region. The method further includes disposing a buffer layer at least covering the scribe line, disposing a dielectric layer including an opening over each chip region, and disposing a bump material to the opening of the dielectric layer and electrically connecting to the active region. The method further includes forming a mold over the substrate, covering the buffer layer and cutting the substrate along the scribe line. Furthermore, the buffer layer includes an elastic modulus less than that of the mold, or the buffer layer includes a coefficient of thermal expansion less than that of the mold.

Abstract: A semiconductor device includes a housing, a substrate housed in and fixed to the housing, and a semiconductor module package disposed on a surface of the substrate. A protrusion is formed on the housing, protrudes towards the substrate, located adjacent to the semiconductor module package, and directly or indirectly urges the substrate in a direction away from the protrusion.

Abstract: A semiconductor light emitting device comprising a light emitting layer disposed between an n-type region and a p-type region is combined with a ceramic layer which is disposed in a path of light emitted by the light emitting layer. The ceramic layer is composed of or includes a wavelength converting material such as a phosphor. Luminescent ceramic layers according to embodiments of the invention may be more robust and less sensitive to temperature than prior art phosphor layers. In addition, luminescent ceramics may exhibit less scattering and may therefore increase the conversion efficiency over prior art phosphor layers.

Abstract: A semiconductor device is provided. The semiconductor device includes a lower layer, an upper layer and an interlayer via. The lower layer includes a lower substrate, lower electronic devices, metallization elements and contact elements. One of the lower electronic devices includes a field effect transistor (FET), lower contacts and spacers interposed between the FET and the lower contacts. At least one of the contact elements is electrically coupled between a metallization element and one of the lower contacts to form a stack. The upper layer includes an upper substrate and upper electronic devices. One of the upper electronic devices includes an FET, upper contacts and spacers interposed between the FET and the upper contacts. The upper substrate and one of the upper contacts define a through-hole aligned with the stack. The interlayer via extends through the through-hole to electrically couple the stack and the one of the upper contacts.

Abstract: Alignment between memory openings through multiple tier structures can be facilitated employing a temporary landing pad. The temporary landing pad can have a greater area than the horizontal cross-sectional area of a first memory opening through a first tier structure including a first alternating stack of first insulating layers and first spacer material layers. An upper portion of a first memory film is removed, and a sidewall of an insulating cap layer that defines the first memory opening can be laterally recessed to form a recessed cavity. A sacrificial fill material is deposited in the recessed cavity to form a sacrificial fill material portion, which functions as the temporary landing pad for a second memory opening that is subsequently formed through a second tier structure including second insulating layers and second spacer material layers. A memory stack structure can be formed through the first and second tier structures.

Abstract: A semiconductor device includes a semiconductor chip having a wire and a passivation film formed on the outermost surface with an opening partially exposing the wire. A resin layer is stacked on the semiconductor chip and provided with a through-hole in a position opposed to a portion of the wire facing the opening. A pad is formed on a peripheral portion of the through-hole in the resin layer and in the through-hole so that an external connection terminal is arranged on the surface thereof. The peripheral portion of the resin layer is formed more thickly than the remaining portion of the resin layer other than the peripheral portion.

Abstract: A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.

Abstract: A compound semiconductor integrated circuit comprising a first substrate; a first electronic component formed on top of said first substrate; a layer of a first dielectric material formed on top of said first substrate and including said first electronic component, said layer of a first dielectric material comprising a recess exposing a first region of said first substrate; and a layer of a second dielectric material attached to said first substrate on top of said first region of said first substrate after manufacturing of said layer of a second dielectric material, said layer of a second material comprising a second electronic component.

Abstract: Disclosed an organic electroluminescent device and a method for fabricating the same. The device may include a thin film transistor disposed on a substrate; a first electrode formed for each pixel on the thin film transistor; a first pixel define layer formed to cover an edge portion of the first electrode; a second pixel define layer formed on the first pixel define layer; an organic layer formed on the first electrode; and a second electrode formed on the organic layer.

Abstract: A chip capacitor according to the present invention includes a substrate, a pair of external electrodes formed on the substrate, a capacitor element connected between the pair of external electrodes, and a bidirectional diode connected between the pair of external electrodes and in parallel to the capacitor element. Also, a circuit assembly according to the present invention includes the chip capacitor according to the present invention and a mounting substrate having lands, soldered to the external electrodes, on a mounting surface facing a front surface of the substrate.

Abstract: The technique described herein can form a semiconductor device having a favorable characteristic over a flash memory with a 3D structure. Provided is a method of manufacturing a semiconductor device, including: (a) forming a stacked structure having an insulating film and a sacrificial film stacked therein by performing a combination a plurality of times, the combination including: (a-1) forming the insulating film on a substrate; (a-2) forming the sacrificial film on the insulating film; and (a-3) modifying at least one of the insulating film and the sacrificial film to reduce a difference between stresses of the insulating film and the sacrificial film.

Abstract: A charge-coupled device (CCD) image sensor is provided. The CCD image sensor may include an array of photosensors that transfer charge to multiple vertical CCD shift registers, which then in turn transfer the charge to a horizontal CCD shift register. The horizontal CCD shift register then feeds an output buffer circuit. The output buffer circuit can include a load transistor implemented using a buried-channel drain (BCD) structure. The load transistor may include a gate conductor, a source diffusion region, a drain diffusion region, and a buried-channel drain region that at least partially extends under the gate conductor. The BCD region may be formed before or after the formation of the gate conductor. If desired, the BCD region can also be formed at the source edge. An image sensor configured in this way can exhibit higher source-drain breakdown voltages, enhanced amplifier gain, and reduced amplifier glow.

Abstract: A semiconductor device includes an IGBT region with a bottom-body region on a front surface side of an IGBT drift region, an IGBT barrier region on a front surface side of the bottom-body region, and a top-body region on a front surface side of the IGBT barrier region. A diode region is include with a bottom-anode region on a front surface side of the diode drift region, a diode barrier region on a front surface side of the bottom-anode region, a top-anode region on a front surface side of the diode barrier region, and a pillar region extending from the front surface of the semiconductor substrate, piercing the top-anode region, and reaching the diode barrier region, and connected to the front surface electrode and the diode barrier region. An impurity concentration of the top-body region is lower than an impurity concentration of the bottom-anode region.

Abstract: A display device includes a plurality of pixels each including a light emitting region; and a light blocking layer provided on a side of the plurality of pixels on which light is output. In each of the plurality pixels, the light blocking layer has a plurality of openings allowing light from the light emitting region to be output. In one embodiment, in the light blocking layer, the openings adjacent to each other may be located line-symmetrically. In one embodiment, in the light blocking layer, the openings adjacent to each other may be located point-symmetrically.

Abstract: An optoelectronic component includes a semiconductor layer structure having a quantum film structure, and a p-doped layer arranged above the quantum film structure, wherein the p-doped layer includes at least one first partial layer and a second partial layer, and the second partial layer has a higher degree of doping than the first partial layer.