Abstract: A semiconductor thin film is formed having a lateral growth region which is a collection of columnar or needle-like crystals extending generally parallel with a substrate. The semiconductor thin film is illuminated with laser light or strong light having equivalent energy. As a result, adjacent columnar or needle-like crystals are joined together to form a region having substantially no grain boundaries, i.e., a monodomain region which can substantially be regarded as a single crystal. A semiconductor device is formed by using the monodomain region as an active layer.

Abstract: A buried bipolar junction is provided in a floating gate transistor flash memory device. During a write operation electrons are injected into a surface depletion region of the memory cell transistors. These electrons are accelerated in a vertical electric field and injected over a barrier to a floating gate of the cells.

Abstract: A submount substrate for mounting a light emitting device and a method of fabricating the same, wherein since a submount substrate for mouthing a light emitting device in which a Zener diode device is integrated can be fabricated by means of a silicon bulk micromachining process without using a diffusion mask, some steps of processes related to the diffusion mask can be eliminated to reduce the manufacturing costs, and wherein since a light emitting device can be flip-chip bonded directly to a submount substrate for a light emitting device in which a Zener diode device is integrated, a process of packaging the light emitting device and the voltage regulator device can be simplified.

Abstract: The active pixel includes a photodiode, a transfer gate, and a reset transistor. The photodiode is substantially covered with an overlying structure, thus protecting the entire surface of the photodiode from damage. This substantially eliminates potential leakage current sources, which result in dark current. In one embodiment, the photodiode is covered by a FOX region in combination with the transfer gate.

Abstract: A semiconductor integrated circuit effectively makes use of wiring channels of wiring formed by a damascene method. When first cells are used, since the M1 power source lines are laid out at positions spaced away from a boundary between the cells, the power source lines are not combined in laying out a semiconductor integrated circuit. As a result, the width of the power source lines is not changed. Accordingly, an interval between the line and a line which is arranged close to the line, determined in response to a line width of the lines, can satisfy a design rule; and, hence, the reduction of the wiring channels can be obviated, whereby the supply rate of the wiring channels can be enhanced, and, further, the integrity of a semiconductor chip can be enhanced.

Abstract: A chip package structure including a lead frame, at least one first bonding wire, at least one second bonding wire, third bonding wires and an encapsulant is provided. The lead frame includes a die pad, inner leads and at least one bus bar, wherein the bus bar is disposed therebetween and has a down-set with a height difference from the inner leads. The inner leads are disposed around the die pad. The chip disposed on the die pad has at least one first contact and second contacts. The first bonding wire electrically connects the first contact to the bus bar. The second bonding wire electrically connects the bus bar to one of the inner leads. The third bonding wires electrically connect the other of the inner leads to the second contacts. The lead frame, the chip, the bonding wires are wrapped inside the encapsulant.

Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.

Abstract: A bi-directional transient voltage suppression (“TVS”) device (101) includes a semiconductor die (201) that has a first avalanche diode (103) in series with a first rectifier diode (104) connected cathode to cathode, electrically coupled in an anti-parallel configuration with a second avalanche diode (105) in series with a second rectifier diode (106) also connected cathode to cathode. All the diodes of the TVS device are on a single semiconductor substrate (301). The die has a low resistivity buried diffused layer (303) having a first conductivity type disposed between a semiconductor substrate (301) having the opposite conductivity type and a high resistivity epitaxial layer (305) having the first conductivity type. The buried diffused layer shunts most of a transient current away from a portion of the epitaxial layer between the first avalanche diode and the first rectifier diode, thereby reducing the clamping voltage relative to the breakdown voltage.

Abstract: A high-density electrical package utilizing an array of high performance demountable electrical contacts such as UEC, T-Spring, F-Spring and their equivalent contained in a carrier in the form of an interposer between one or more components and a substrate. The carrier is made of a thermally conductive metal or contains thermally conductive metal to provide heat-spreading or dissipation functions in addition to the function of the retention and alignment of the electrical contacts. The above interposer is used for chip attach for a single chip or a stack of chips in the package. The interposer provides electrical connections through individual electrical contact to another chip or to the substrate of the package. It provides also the heat spreading or dissipation function to the chips connected thermally to a particular interposer. The interposer can further be connected thermally to an external heat spreader when necessary.

Abstract: A silicon-on-insulator (SOI) Read Only Memory (ROM), and a method of making the SOI ROM. ROM cells are located at the intersections of stripes in the surface SOI layer with orthogonally oriented wires on a conductor layer. Contacts from the wires connect to ROM cell diodes in the upper surface of the stripes. ROM cell personalization is the presence or absence of a diode and/or contact.

Abstract: A submount substrate for mounting a light emitting device and a method of fabricating the same, wherein since a submount substrate for mouthing a light emitting device in which a Zener diode device is integrated can be fabricated by means of a silicon bulk micromachining process without using a diffusion mask, some steps of processes related to the diffusion mask can be eliminated to reduce the manufacturing costs, and wherein since a light emitting device can be flip-chip bonded directly to a submount substrate for a light emitting device in which a Zener diode device is integrated, a process of packaging the light emitting device and the voltage regulator device can be simplified.

Abstract: The invention includes a method of forming a metal-comprising mass for a semiconductor construction. A semiconductor substrate is provided, and a metallo-organic precursor is provided proximate the substrate. The precursor is exposed to a reducing atmosphere to release metal from the precursor, and subsequently the released metal is deposited over the semiconductor substrate. The invention also includes capacitor constructions, and methods of forming capacitor constructions.

Abstract: The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

Abstract: An organic light emitting diode display includes an insulating layer, a stress buffer disposed on the insulating layer, a first electrode disposed on the stress buffer, an organic light emitting member disposed on the first electrode, and a second electrode disposed on the organic light emitting member.

Abstract: An object of the present invention is to provide a semiconductor device using a cheap glass substrate, capable of corresponding to the increase of the amount of information and further, having a high performance and an integrated circuit capable of operating at a high rate. A variety of circuits configuring an integrated circuit are formed on a plurality of glass substrates, the transmission of a signal between the respective glass substrates is performed by what is called an optical interconnect using an optical signal. Concretely, alight emitting element is provided on the output side of a circuit disposed on the upper stage formed on one glass substrate, and a photo-detecting element is formed so as to oppose to the relevant light emitting element on the input side of a circuit disposed on the rear stage formed on another glass substrate.

Abstract: A porogen material for forming a dielectric porous film. The porogen material may include a silicon based dielectric precursor and a silicon containing porogen. The porous film may have a substantially uniform dielectric constant value throughout. Methods of forming the porous film as well as semiconductor devices employing circuit features isolated by the porous film are also present.

Abstract: A bipolar transistor includes a collector located over a substrate; and a heat conductive path connecting the substrate to the collector. The heat conductive path is filled with a heat conductive material such as metal or polysilicon. In one embodiment the heat conductive path runs through the collector to extract heat from the collector and drain it to the substrate. In alternate embodiments, the transistor can be a vertical or a lateral device. According to another embodiment, an integrated circuit using BiCMOS technology comprises pnp and npn bipolar transistors with heat conduction from collector to substrate and possibly p-channel and n-channel MOSFETS. According to yet another embodiment, a method for making a transistor in an integrated network comprises steps of etching the heat conducting path through the collector and to the substrate and fill with heat conductive material to provide a heat drain for the transistor comprising the collector.

Abstract: Conductive straps are connected to a subset of word lines of a memory device. Alternatively, first conductive straps are respectively connected only to first portions of first word lines of a memory device, and second conductive straps are respectively connected only to second portions of second word lines of the memory device, where each first word line is adjacent at least one second word line. One or more contacts can be used to connect a conductive strap to its respective word line.

Abstract: Electroless plating can be utilized to form electrical interconnects associated with semiconductor substrates. For instance, a semiconductor substrate can be formed to have a dummy structure thereover with a surface suitable for electroless plating, and to also have a digit line thereover having about the same height as the dummy structure. A layer can be formed over the dummy structure and digit line, and openings can be formed through the layer to the upper surfaces of the dummy structure and digit line. Subsequently, a conductive material can be electroless plated within the openings to form electrical contacts within the openings. The opening extending to the dummy structure can pass through a capacitor electrode, and accordingly the conductive material formed within such opening can be utilized to form electrical contact to the capacitor electrode.

Abstract: Disclosed is a device which comprises a substrate, a plurality of signal output terminal electrodes provided on the substrate, a plurality of signal input terminal electrodes provided on the substrate, and a display driver IC having input terminals thereof connected to the signal input terminal electrodes and output terminals thereof connected to the signal output terminal electrodes. A plurality of output terminals (first, third, fifth, . . . (i+1)th, and (n?1)th) are included on a first side of the display driver IC facing the signal input terminal electrodes. A second side on an opposite side of the first side faces the signal input terminal electrodes. Input terminals 22 are included in at least one segment of the second side, and output terminals (second, fourth, sixth, ith, jth, (j+2)th, (n?2)th, and nth) are included in at least one portion of the remaining segment of the second side.