Abstract: The invention concerns a magnetic memory, whereof each memory point consists of a magnetic tunnel junction (60), comprising: a magnetic layer, called trapped layer (61), whereof the magnetization is rigid; a magnetic layer, called free layer (63), whereof the magnetization may be inverse; and insulating layer (62), interposed between the free layer (73) and the trapped layer (71) and respectively in contact with said two layers. The free layer (63) is made with an amorphous or nanocrytallized alloy based on rare earth or a transition metal, the magnetic order of said alloy being of the ferromagnetic type, said free layer having a substantially planar magnetization.

Abstract: A New Phosphor-converted LED Device (“NPCLD”) is disclosed. The NPCLD may include a lens over a phosphor body, in which the lens and the phosphor body each have a substantially convex upper surface. The NPCLD may alternatively include first and second lenses, the first lens having a substantially flat interface with a phosphor body.

Abstract: Low power magnetoresistive random access memory elements and methods for fabricating the same are provided. In one embodiment, a magnetoresistive random access device has an array of memory elements. Each element comprises a fixed magnetic portion, a tunnel barrier portion, and a free SAF structure. The array has a finite magnetic field programming window Hwin represented by the equation Hwin?(Hsat??sat)?(Hsw+?sw), where Hsw is a mean switching field for the array, Hsat is a mean saturation field for the array, and Hsw for each memory element is represented by the equation HSW??{square root over (HkHSAT)}, where Hk represents a total anisotropy and HSAT represents an anti-ferromagnetic coupling saturation field for the free SAF structure of each memory element. N is an integer greater than or equal to 1. Hk, HSAT, and N for each memory element are selected such that the array requires current to operate that is below a predetermined current value.

Abstract: A method of making a transistor driver circuit with a plurality of transistors, each having source and drain regions formed in a substrate. At least first and second interconnect layers are formed on top of the substrate. A first plurality of contacts connect the source regions to one of the first or second interconnect layers. A second plurality of contacts connect the drain regions to the other of the first or second interconnect layers. The first and second interconnect layers cover a region above the substrate area in which the plurality of transistors reside so as to achieve a low ohmic result. The second interconnect layer has openings therein for one of the respective first or second plurality of contacts to pass therethrough and couple to the at least one first interconnect layer. Either the first or second interconnect layers can function as an input or output for the circuit.

Abstract: A low cost semiconductor nonvolatile memory device capable of high speed programming, using an inversion layer as the wiring, and a manufacturing method for that device. The semiconductor memory device includes an auxiliary electrode at a position between and in parallel with the source and drain regions and with no position overlap versus the source region and the drain region formed mutually in parallel; wherein the auxiliary electrode for hot electron source injection is utilized as the auxiliary electrode for programming (writing); and an inversion layer formed below the auxiliary electrode is utilized as the source region or as the drain region during the read operation.

Abstract: A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a metal pillar, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The metal pillar includes tapered sidewalls with first and second sidewall portions and a spike, and the first and second sidewall portions are concave arcs that are adjacent to one another at the spike.

Abstract: A nano-electrode or nano-wire may be etched centrally to form a gap between nano-electrode portions. The portions may ultimately constitute a single electron transistor. The source and drain formed from the electrode portions are self-aligned with one another. Using spacer technology, the gap between the electrodes may be made very small.

Abstract: One embodiment of a microelectronic device includes a movable plate including a lower surface, a bump positioned on the lower surface, and an anti-stiction coating positioned only on the bump.

Abstract: A field-effect semiconductor element implemented with a fewer number of elements and a reduced area and capable of storing data by itself without need for cooling at a cryogenic temperature, and a memory device employing the same. Gate-channel capacitance is set so small that whether or not a trap captures one electron or hole can definitely and distinctively be detected in terms of changes of a current of the semiconductor FET element. By detecting a change in a threshold voltage of the semiconductor element brought about by trapping of electron or hole in the trap, data storage can be realized at a room temperature.

Abstract: After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon nitride is removed, thereby a contact hole is formed. A contact plug is buried into this contact hole. With this arrangement, the contact plug can be formed without using a diffusion layer contact pattern. At the same time, the periphery of the contact plug substantially coincides with a boundary between the element isolation region and the active region. Accordingly, the active region can be reduced.

Abstract: A nitride semiconductor device, which includes a III-V Group nitride semiconductor layer being composed of a III Group element consisting of at least one of a group containing of gallium, aluminum, boron and indium and V Group element consisting of at least nitrogen among a group consisting of nitrogen, phosphorus and arsenic, including a first nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on a substrate, a second nitride semiconductor layer including the III-V Group nitride semiconductor layer being deposited on the first nitride semiconductor and not containing aluminum and a control electrode making Schottky contact with the second nitride semiconductor layer wherein the second nitride semiconductor layer includes a film whose film forming temperature is lower than the first nitride semiconductor layer.

Abstract: A package for an integrated circuit (IC) die comprises a substrate and a lid. The substrate has an upper surface facing an interior of the package and a lower surface facing an exterior of the package. The upper surface of the substrate carries an IC die and provides electrical connections from the IC die to the lower surface of the substrate. The lid includes an outer lid and an inner lid. The inner lid is positioned over the IC die and is in thermal communication with the IC die. The inner lid is formed of a material suitable for conducting heat away from the IC die. The outer lid is attached to the upper surface of the substrate. A gap extends between the outer lid and inner lid.

Abstract: An integrated circuit package includes a package substrate with a plurality of pins coupled to a semiconductor chip having a plurality of bond pads, some of which are ic bond pads coupled to an integrated circuit formed on the semiconductor chip and others of which are floating bond pads that are isolated from the integrated circuit. The plurality of pins include active pins coupled to active bond pads and dummy (non-coupled) pins coupled to floating bond pads. The floating bond pads are formed of interconnect materials also used to form the integrated circuit. BGA or flip-chip IC packages may be used and a method is provided for forming the IC package. The floating bond bad design prevents ESD (electrostatic discharge) from damaging the active device due to an adjacent non-coupled pin of the package being subjected to ESD.

Abstract: A first semiconductor element and second semiconductor element are bonded via die-bonding material. A first electrode of the first semiconductor element and a third electrode are joined, by means of flip-chip bonding, to a semiconductor carrier that has the third electrode on the one face of the semiconductor carrier and a fourth electrode on the perimeter of the other face of the semiconductor carrier. The bonding pad of the second semiconductor element and the fourth electrode of the semiconductor carrier are connected via fine metal wire by means of wire bonding. The periphery of the first semiconductor element and the wiring portion of the fine metal wire are filled with insulating sealing resin between the semiconductor carrier and second semiconductor element and the sealing fill region for the sealing resin is formed substantially the same as the external dimensions of the second semiconductor element.

Abstract: A submount that enables the reliable mounting of a semiconductor light-emitting device on it, and a semiconductor unit incorporating the submount. A submount 3 comprises (a) a substrate 4; and (b) a solder layer 8 formed on the top surface 4f of the substrate 4. The solder layer 8 before melting has a surface roughness, Ra, of at most 0.18 ?m. It is more desirable that the solder layer 8 before melting have a surface roughness, Ra, of at most 0.15 ?m, yet more desirably at most 0.10 ?m. A semiconductor unit 1 comprises the submount 3 and a laser diode 2 mounted on the solder layer 8 of the submount 3.

Abstract: A display device includes a pixel region having a plurality of pixels and a peripheral circuit region disposed at a periphery of the pixel region for driving the pixels. The peripheral circuit region includes transistors fabricated from polycrystalline semiconductor and having a semiconductor crystalline grain of a first kind in a channel region thereof, wherein a grain size of the semiconductor crystalline grain of the first kind is at least 3 ?m. The pixel region includes transistors fabricated from polycrystalline semiconductor and having a semiconductor crystalline grain of a second kind in a channel region thereof, wherein a grain size of the semiconductor crystalline grain of the second kind is at least 0.05 ?m.

Abstract: A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.

Abstract: TFTs arranged in various circuits have structures that are suited for circuit functions, in order to improve operation characteristics and reliability of the semiconductor device, to lower consumption of electric power, to decrease the number of steps, to lower the cost of production and to improve the yield. The gradient of concentration of impurity element for controlling the conduction type in the LDD regions 622 and 623 of the TFT is such that the concentration increases toward the drain region. For this purpose, a tapered gate electrode 607 and a tapered gate-insulating film 605 are formed, and the ionized impurity element for controlling the conduction type is added to the semiconductor layer through the gate-insulating film 605.

Abstract: A LED structure including an epitaxy substrate, a semiconductor layer, a first bonding pad and a second bonding pad, is provided. The epitaxy substrate has a through hole and the semiconductor layer is disposed on the epitaxy substrate. The semiconductor layer includes a first type doped semiconductor layer, a light-emitting layer and a second type doped semiconductor layer. The first type doped semiconductor layer is disposed on the epitaxy substrate, while the light-emitting layer is disposed between the first type and second type doped semiconductor layers. The first bonding pad is disposed in the through hole and electrically connected to the first type doped semiconductor layer, while the second bonding pad is disposed on the second type doped semiconductor layer.