Abstract: A grid to vehicle system is described. In some examples, the system selectively controls one or more electric vehicles connected to an electric grid based on conditions associated with the electric grid. For example, the system may control charging operations of the electric vehicles based on load balancing conditions associated with the electric grid, based on cost conditions associated with electric power provided by the electric grid, and so on.

Abstract: Systems and methods are provided for simulating quantile behavior of a physical system. A plurality of parameter samples to a physical system are accessed and a subset of the parameter samples are identified, each of the plurality of parameter samples including a variation of parameters for the physical system. The physical system is simulated based on the subset of the parameter samples to generate simulation results, each of the subset of the parameter samples corresponding to a respective one of the simulation results. A neural network is trained to predict the simulation results based on the subset of the parameter samples.

Abstract: A method includes detecting submission of a first quantum circuit for compilation, the first quantum circuit comprising a first set of quantum logic gates; generating a first gate index, the first gate index comprising an ordered table of a subset of the set of quantum logic gates, each quantum logic gate of the subset of quantum logic gates including a corresponding set of qubits acted on by the quantum logic gate; comparing the first gate index with a second gate index to determine a structural equality of the first quantum circuit and the second quantum circuit; and parameterizing, in response to determining a structural equality of the first quantum circuit and the second quantum circuit, a first set of parameters of a second set of quantum logic gates of the second quantum circuit with a second set of parameters of the first set of quantum logic gates.

Abstract: Disclosed are methods, systems, and articles of manufacture for determining layout equivalence between a plurality of versions of a single layout of a multi-fabric electronic design. These techniques identify a first version and a second version of a layout of an electronic design that spans across multiple design fabrics. One or more collaborative comparator modules are executed to determine whether the first version is identical to or different from the second version of the layout. These techniques further modify the first version or the second version of the layout with discrepancy annotation.

Abstract: According to one embodiment, there is provided an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks.

Abstract: Provided are a BLUETOOTH headset, a charging cabin and a charging system thereof. The BLUETOOTH headset includes: a headset charging interface circuit, a control circuit, a level shifting circuit and a chip module. The headset charging interface circuit includes a detecting terminal connected to a power supply voltage terminal of the BLUETOOTH headset through the control circuit. When the detecting terminal is connected to a detecting pin of the charging cabin, a voltage of the detecting terminal is shifted from a first voltage provided by the power supply voltage terminal to a second voltage provided by the detecting pin of the charging cabin to trigger the control circuit to output a first level signal to the level shifting circuit, and then the first level signal is shifted to a power-off signal through the level shifting circuit to trigger the chip module to power off the BLUETOOTH headset.

Abstract: A computing system implementing a functional safety validation tool to simulate a circuit design having a digital portion and an analog portion, and inject a fault into the digital portion of a simulated circuit design, which propagates towards alarm logic configured to detect the injected fault. When the injected fault propagates to a boundary between the digital portion and the analog portion, the functional safety validation tool can perform a parallel simulation of the analog portion, which propagates the injected fault from the boundary through the analog portion to an output. The functional safety validation tool can determine whether the analog portion of the circuit design suppresses the injected fault based on a value at the output. The functional safety validation tool can generate a fault coverage presentation identifying a diagnostic coverage of the alarm logic based on whether the injected fault was suppressed.

Abstract: A method for fabricating a semiconductor chip includes controlling a chip testing device to measure, for each bit of a plurality of bits in the semiconductor chip, mask dimensions for a feature to determine variations of the feature within each bit. Based on the variations a probability of each bit being “0” or “1” is generated to provide predicated probabilities. Based on the predicted probabilities, each bit of the plurality of bits is grouped and a subset of bits is selected to provide a subset of predicted results. The chip testing unit is controlled to measure whether each bit of the subset of bits is in a state is “0” or “1” to provide measured results. The subset of predicted results is compared with the measured results to provide a comparison. Based on the comparison, determination is made that the semiconductor chip has been fabricated using an altered mask.

Abstract: Metrology overlay targets are provided, as well as method of monitoring process shortcomings. Targets comprise periodic structures, at least one of which comprising repeating asymmetric elements along a corresponding segmentation direction of the periodic structure. The asymmetry of the elements may be designed in different ways, for example as repeating asymmetric sub-elements along a direction perpendicular to the segmentation direction of the elements. The asymmetry of the sub-elements may be designed in different ways, according to the type of monitored process shortcomings, such as various types of hot spots, line edge shortening, process windows parameters and so forth. Results of the measurements may be used to improve the process and/or increase the accuracy of the metrology measurements.

Abstract: A module-based framework evaluates designs of advanced start stop systems, particularly 12V advanced start stop systems. The framework separates vehicle and battery analysis and uses a power profile to evaluate different designs of the vehicles and batteries. Particularly, the framework can evaluate different battery solutions and compare performances as a function of drive cycles, motor size, and electrical loads. In addition to modeling, actual batteries are tested for the same power inputs for validating performance differences. This framework identifies performance limiting components for determination of the vehicle system component optimization.

Abstract: A method may designing electronic circuits is provided. The method may include generating a first user interface for displaying, at a client, a plurality of graphical elements for creating a state diagram. A scaffold may be added to the state diagram in response to the scaffold being selected from the plurality of graphical elements. A first state bubble may be attached to the scaffold in response to the first state bubble being selected from the plurality of graphical elements. A dimension of the scaffold and/or a position of the first state bubble on the scaffold may be adjusted in response to a second state bubble being added and/or removed from the state diagram. A second user interface may be generated for displaying, at the client, the state diagram. Related systems and articles of manufacture, including computer program products, are also provided.

Abstract: Systems, methods, media, and other such embodiments described herein relate to insertion of test points in circuit design and associated test coverage for a circuit design. One embodiment involves a circuit design with a plurality of circuit elements and a plurality of clock gating logic elements. A first node coupled to a first circuit element is selected for insertion of a test point circuit element. Elements of the design are identified that contribute to a data state of the first node, and clock elements for these identified design elements are traced. An ungated clock input node from this trace is selected, and the clock input from this node is connected to the test point circuit element. The circuit design is then updated with this connection. In various embodiments when multiple ungated clock input nodes are identified by the trace, additional criteria are used to select among the ungated clock input nodes.

Abstract: A hierarchical power verification system and method creates abstract models of power behavior of modules that it successfully verifies. The abstract models simplify the module definition by omitting internal module details but provide sufficient information for power verification of higher level modules that incorporate this abstracted module. Design blocks are replaced with these abstract power models, resulting in reduced run-time and memory requirements. The power models can include power switches inside the block, related supplies of logic ports, supply power states, system power states, power management devices such as isolation logic and level shifters, feed-through and floating ports. The power model may be expressed either in UPF or as a combination of liberty model and UPF. After replacing modules with abstracted models the HPVS can quickly verify an entire SoC with a small memory footprint.

Abstract: A system configuration creation supporting device includes: a display unit to display a network configuration diagram in which a first object and a second object within a first network level of a plurality of network levels are arranged, the first object being an image representing a network, the second object being an image representing a node connected to the network; and a data processing unit to calculate, on the basis of the first network level, coordinates for displaying the first and second objects on the display unit, and display on the display unit the network configuration diagram according to the first network level on the basis of the calculated coordinates.

Abstract: A chip design environment is disclosed which accepts application specific processing, memory and IO elements and declarative specification of function, cost and performance of peripheral, low-level and infrastructural elements and of overall design and generates synthesizable module RTLs and relevant place-and-route constraints. The generated elements include the network interconnecting all the elements, a programming memory consistency model and its coherence protocol, allocation and scheduling processes realizing run-time inference of optimal parallel execution and processes for control of coherence action and prefetch intensity, task-data migration, voltage-frequency scaling and power-clock gating. The environment employs knowledge bases, models to predict performance and to assign confidence scores to predictions and, in turn, the predictions to explore space of topology, architecture, composition, etc options.

Abstract: A static timing analysis controller includes a feedback loop identification module that identifies invariable flip flop feedback loops of an integrated circuit design, and adds the identified feedback loops to false path lists. The static timing analysis controller then performs timing update operations and identifies hold violations based on the invariable flip flop feedback loops included in the false path list. In turn, the static timing analysis controller identifies reduced or less pessimistic numbers of hold violations, resulting in fewer buffers added to the integrated circuit design.

Abstract: Simultaneous automatic placement and routing speeds up implementation an integrated circuit layout and improves the resulting layout such that the layout is more compact, has reduced parasitics, and has improved circuit performance characteristics (e.g., power, frequency, propagation delay, gain, and stability). A technique generates solutions based on random normalized polish expression, and includes cost considerations based on routing of interconnect.

Abstract: The present disclosure provides a system and a method for quickly diagnosing, classifying, and sampling in-line defects based on a CAA pre-diagnosis database. The method includes the steps of obtaining a design layout of an object and a defect data of an important process stage of the object, obtaining a pre-diagnosis data group related to the design layout from a CAA pre-diagnosing database, and judging a killer defect index and a failure risk level of the defect data according to the pre-diagnosis data group.

Abstract: The invention concerns a circuit for charging a battery by means of a photovoltaic module, including: input and output terminals intended to be respectively coupled to the module and to the battery; a converter including input and output terminals respectively coupled to the input and output terminals of the charging circuit; a control circuit including power supply terminals coupled to the output terminals of the charging circuit; a switch coupling one of the output terminals of the converter to one of the output terminals of the charging circuit; and a detection circuit configured, when the voltage between output terminals of the charging circuit exceeds a threshold, to send an order to turn off the switch and stop the converter for a predetermined period.

Abstract: Metrology target design methods and verification targets are provided. Methods include using OCD data related to designed metrology target(s) as an estimation of a discrepancy between a target model and a corresponding actual target on a wafer, and adjusting a metrology target design model to compensate for the estimated discrepancy. The dedicated verification targets may include overlay target features and be size optimized to be measurable by an OCD sensor, to enable compensation for inaccuracies resulting from production process variation. Methods also include modifications to workflows between manufacturers and metrology vendors which provide enabled higher fidelity metrology target design models and ultimately higher accuracy of metrology measurements.