Abstract: A high-voltage battery for a motor vehicle, the operating voltage of which is greater than 12 V, in particular, greater than 50 V, having two power connections at a high-voltage network power system of the motor vehicle, which can be connected without voltage through first safety contactors provided inside a housing of the high-voltage battery, and storage cells for electrical energy that are connected to the power connections via the first safety contactors. The high-voltage battery additionally has two charging terminals, which are connected to the storage cells by circumventing the first safety contactors by way of charging lines.

Abstract: A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to extend parallel to each other. Each of the linear-shaped diffusion fins is defined to project upward from the substrate along their extent in the first direction. A number of gate level structures are defined to extend in a conformal manner over some of the number of linear-shaped diffusion fins. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins extend in a second direction that is substantially perpendicular to the first direction. Portions of each gate level structure that extend over any of the linear-shaped diffusion fins form gate electrodes of a corresponding transistor. The diffusion fins and gate level structures can be placed in accordance with a diffusion fin virtual grate and a gate level virtual grate, respectively.

Abstract: A method for performing graph-based static timing analysis comprises reading in a design of an integrated circuit having a subset of timing paths, each timing path of the subset having a common point, wherein the common point is identical for all timing paths of the subset. The method comprises initiating a timing signal at the common point, the timing signal propagating along a plurality of timing arcs of the subset. The timing signal has a plurality of attributes varying with the propagation including a depth value and/or a distance value. The method comprises determining a derating factor for a delay of at least one of the plurality of timing arcs depending on the depth and/or the distance value of the timing signal at a pin of said at least one timing arc, and generating a timing report based on the derating factor.

Abstract: A matrix is produced for a semiconductor design. Interactions between mask edges in forming semiconductor shapes are determined and a graph created that shows those interactions. The graph is then partitioned into groups using a coloring algorithm, with each group representing one or more non-interacting mask edges. A lithography simulation is performed for each group, with the edges of that group perturbed, but the edges of other groups unmoved. The partial derivatives are calculated for the edges of a group based on the simulation with those edges perturbed, and used to populate locations in a Jacobian matrix. The Jacobian matrix is then used to solve an Optical Proximity Correction (OPC) problem by finding a mask edge correction vector for a given wafer targeting error vector.

Abstract: A charging facility includes a primary coil, magnets arranged relative to the primary coil in a pattern such that fields generated by the magnets can be used to position a vehicle relative to the primary coil, and a controller. Some of the magnets have a predefined polarity signature encoding data regarding an identify of the primary coil. The controller is programmed to receive information from or provide information to the vehicle about the predefined polarity signature.

Abstract: Systems and methods for modeling a bus for a system design are provided. In an embodiment, the method operates by accepting a virtual bus model, wherein the model simulates behavior for a bus master and slave device, such that the model accurately simulates the timing and behavior of the transfer of data from master to slave, and, from slave to master devices. The method routes a transaction issued by the master device to the slave device. The transaction has storage for transaction data, or a pointer to transaction data, to be transferred through the transaction. The transaction data is transferred in one or more data payloads and the sender of data sets the length of data payloads to be returned. The data payloads are sent from the sender of data to the receiver of data and may contain one or more bus data beats. This method accurately models the bus timing and behavior of the delivery of one or more data beats as one data payload.

Abstract: A method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic apparatus, the method including: obtaining a first source of the lithographic apparatus; classifying the first source into a class among a plurality of possible classes, based on one or more numerical characteristics of the first source, using a machine learning model, by a computer; determining whether the class is among one or more predetermined classes; only when the class is among the one or more predetermined classes, adjusting one or more source design variables to obtain a second source.

Abstract: A method of manufacturing a printed circuit board (PCB) includes determining a weft direction of the PCB, and defining a routing design of differential pairs. The routing design is designed to have a fixed region in the weft direction. The method further includes manufacturing the PCB according to the routing design.

Abstract: Provided is a battery balancing apparatus and method including determining state information of a battery unit based on battery quantity data of the battery unit, determining a balancing parameter of the battery unit based on a range comprising the state information, and controlling a balancing unit based on the balancing parameter.

Abstract: An offloading engine integrated circuit that includes soft processors may be implemented using an aggregated profiler and a soft processor system generation tool. In particular, the aggregated profiler may generate a suggested configuration for soft processors within the integrated circuit. The soft processor system generation tool may use inputs based on the suggested configuration to generate a configuration bit stream that is used to configure the integrated circuit. Soft processors within the integrated circuits may be arranged in soft processors columns. Parameters for the soft processors and the soft processor columns may be dynamically reconfigured. The parameters may include sizes for each soft processor column, a number of soft processor columns, types (e.g., processor architecture types) of each processor. Multiple soft processor columns may also be grouped together to complete a single task. Interface circuitry may regulate information flow to and from the soft processor columns.

Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes.

Abstract: A computer-implemented method includes modeling, using the computer, a photoresist profile in accordance with a magnitude of a gradient of an inhibitor concentration disposed in the photoresist. The photoresist is used during a process to form an integrated circuit. In one embodiment, the computer-implemented method further includes applying the modeled photoresist profile to reduce a distortion in a printed photoresist pattern caused by a response of the photoresist to an electromagnetic wave and/or particle beam during the process.

Abstract: Reducing dynamic power consumption for a circuit can include analyzing, using a processor, a netlist specifying the circuit to determine a block of combinatorial circuitry in a first signal path with at least a threshold amount of switching activity and detecting, using the processor, a second signal path coupled to the block of combinatorial circuitry by a sequential circuit element. The second signal path has a delay that meets a target signal path requirement. Using the processor, the netlist can be modified by subdividing the block of combinatorial circuitry into at least a first portion and a second portion and moving one of the portions from the first signal path to the second signal path, wherein the moving separates the first portion from the second portion by the sequential circuit element.

Abstract: One embodiment provides an electronic device including: a processor; a power supply module coupled to the processor; a receiving antenna coupled to the power supply module, wherein receiving antenna cooperates with a transmitting antenna of a wireless charger to charge the power supply module wirelessly; an inductor arranged with respect to the receiving antenna, wherein the inductor comprises a first wire and a second wire through which a first induced voltage and a second induced voltage are generated respectively; a comparator for comparing the first and second induced voltages; and wherein the processor determines if the receiving antenna is aligned with respect to the transmitting antenna of the wireless charger based upon the comparison of the first and second induced voltages. Other aspects are described and claimed.

Abstract: Systems and methods for validating a circuit design are described. The circuit validation includes determining a subset of checks to apply to a portion of the overall circuit based on the pin type composition of the circuit portion.

Abstract: A computer-implemented method for constructing a design characterized by a double patterning layer is presented. The method includes receiving the design in a memory of the computer when the computer is invoked to construct the design. The method further includes generating, using the computer, a multitude of fill shapes along a multitude of tracks associated with a multitude of net shapes. The multitude of fill shapes and the multitude of net shapes are decomposable into two colors in accordance with a spacing constraint of the double patterning layer.

Abstract: Systems and techniques are described for producing a synthesized IC design that includes design-for-testability (DFT) circuitry. A register-transfer-level (RTL) representation of an IC design can be received, wherein the RTL representation includes functional logic. Next, DFT logic can be added to the RTL representation, and DFT placement guidance for placing the DFT logic can be generated. Synthesis can be performed on the RTL representation to obtain the synthesized IC design, wherein during synthesis, (1) the functional logic and the DFT logic can be placed, wherein the DFT logic is placed based on the DFT placement guidance, (2) scan chains can be inserted and placed, and (3) the DFT logic can be electrically connected with the scan chains.

Abstract: Systems and methods are described for creating a netlist abstraction that provides full-chip context for performing circuit design floorplanning. The netlist abstraction can include a top-level netlist abstraction that corresponds to the top-level portion of the netlist, and a physical block netlist abstraction for each physical block in the circuit design. Each physical block netlist abstraction can retain macros that are in the physical block.

Abstract: Methods and systems for verifying a derived clock using assertion-based verification. The method comprises counting the number of full or half cycles of a fast clock that occur between the rising edge and the falling edge of a slow clock (i.e. during the ON phase of the slow clock); counting the number of full or half cycles of the fast clock that occur between the falling edge and the rising edge of the slow clock (i.e. during the OFF phase of the slow clock); and verifying the counts using assertion-based verification.

Abstract: A method for generating a three-dimensional (3D) computer model of an assembly that includes wiring routing, which includes creating a part data structure that defines a part in a virtual product management system. The part data structure includes a plurality of nodes that define at least 3D part design data, 3D wiring routing design data and wiring routing annotation data of the part. The method includes importing at least the 3D part design data, the 3D wiring routing design data and the wiring routing annotation data to the part data structure from a computer-aided design (CAD) model system and generating a 3D computer model of the assembly. The method also includes transmitting the 3D computer model of the assembly to an electronic end user device.